NUM_VFT_COLUMNS 710 drivers/gpu/drm/amd/powerplay/inc/smu73.h VFT_CELL_t Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 711 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint16_t AvfsGbv [NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 712 drivers/gpu/drm/amd/powerplay/inc/smu73.h uint16_t BtcGbv [NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 782 drivers/gpu/drm/amd/powerplay/inc/smu74.h VFT_CELL_t Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 783 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint16_t AvfsGbv[NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 784 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint16_t BtcGbv[NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 796 drivers/gpu/drm/amd/powerplay/inc/smu74.h VFT_CELL_t Cell[NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 812 drivers/gpu/drm/amd/powerplay/inc/smu74.h VFT_CELL_t Cell[NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 822 drivers/gpu/drm/amd/powerplay/inc/smu74.h uint8_t Static_Voltage_Offset[NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 679 drivers/gpu/drm/amd/powerplay/inc/smu75.h VFT_CELL_t Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 680 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint16_t AvfsGbv [NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 681 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint16_t BtcGbv [NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 685 drivers/gpu/drm/amd/powerplay/inc/smu75.h SCS_CELL_t ScksCell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 715 drivers/gpu/drm/amd/powerplay/inc/smu75.h VFT_CELL_t Cell[NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 720 drivers/gpu/drm/amd/powerplay/inc/smu75.h VFT_CELL_t Cell[NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 725 drivers/gpu/drm/amd/powerplay/inc/smu75.h VFT_CELL_t Cell[NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 730 drivers/gpu/drm/amd/powerplay/inc/smu75.h VFT_CELL_t Cell[NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 740 drivers/gpu/drm/amd/powerplay/inc/smu75.h uint8_t Static_Voltage_Offset[NUM_VFT_COLUMNS]; NUM_VFT_COLUMNS 1743 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c for (i = 0; i < NUM_VFT_COLUMNS; i++) {