NUM_UCLK_DPM_LEVELS 1656 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) NUM_UCLK_DPM_LEVELS 1830 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c while (i < NUM_UCLK_DPM_LEVELS) { NUM_UCLK_DPM_LEVELS 3484 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1; NUM_UCLK_DPM_LEVELS 3508 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) { NUM_UCLK_DPM_LEVELS 2341 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, NUM_UCLK_DPM_LEVELS 3487 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, NUM_UCLK_DPM_LEVELS 333 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) NUM_UCLK_DPM_LEVELS 57 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) NUM_UCLK_DPM_LEVELS 424 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; NUM_UCLK_DPM_LEVELS 49 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) NUM_UCLK_DPM_LEVELS 503 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz NUM_UCLK_DPM_LEVELS 60 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) NUM_UCLK_DPM_LEVELS 588 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz NUM_UCLK_DPM_LEVELS 598 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 NUM_UCLK_DPM_LEVELS 603 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) NUM_UCLK_DPM_LEVELS 604 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) NUM_UCLK_DPM_LEVELS 50 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) NUM_UCLK_DPM_LEVELS 220 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint8_t MemVid[NUM_UCLK_DPM_LEVELS]; /* VID */ NUM_UCLK_DPM_LEVELS 221 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h PllSetting_t UclkLevel[NUM_UCLK_DPM_LEVELS]; /* Full PLL settings */ NUM_UCLK_DPM_LEVELS 222 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h uint8_t MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS]; NUM_UCLK_DPM_LEVELS 53 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) NUM_UCLK_DPM_LEVELS 312 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; NUM_UCLK_DPM_LEVELS 601 drivers/gpu/drm/amd/powerplay/navi10_ppt.c dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1]; NUM_UCLK_DPM_LEVELS 2044 drivers/gpu/drm/amd/powerplay/vega20_ppt.c if (dpm_table->count > NUM_UCLK_DPM_LEVELS) {