NUM_LINK_LEVELS  1255 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	for (i = 0; i < NUM_LINK_LEVELS; i++) {
NUM_LINK_LEVELS  1277 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	pcie_table->count = NUM_LINK_LEVELS;
NUM_LINK_LEVELS  1525 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	while (i < NUM_LINK_LEVELS) {
NUM_LINK_LEVELS  2650 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		if (soft_min_level >= NUM_LINK_LEVELS ||
NUM_LINK_LEVELS  2651 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		    soft_max_level >= NUM_LINK_LEVELS)
NUM_LINK_LEVELS  3361 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		for (i = 0; i < NUM_LINK_LEVELS; i++) {
NUM_LINK_LEVELS   399 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	for (i = 0; i < NUM_LINK_LEVELS; i++)
NUM_LINK_LEVELS   403 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	for (i = 0; i < NUM_LINK_LEVELS; i++)
NUM_LINK_LEVELS   407 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	for (i = 0; i < NUM_LINK_LEVELS; i++)
NUM_LINK_LEVELS    63 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h #define MAX_LINK_LEVEL        (NUM_LINK_LEVELS        - 1)
NUM_LINK_LEVELS   452 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h   uint8_t      PcieGenSpeed[NUM_LINK_LEVELS];
NUM_LINK_LEVELS   453 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h   uint8_t      PcieLaneCount[NUM_LINK_LEVELS];
NUM_LINK_LEVELS   454 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h   uint16_t     LclkFreq[NUM_LINK_LEVELS];
NUM_LINK_LEVELS    62 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h #define MAX_LINK_LEVEL        (NUM_LINK_LEVELS        - 1)
NUM_LINK_LEVELS   625 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h   uint8_t      PcieGenSpeed[NUM_LINK_LEVELS];           ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4
NUM_LINK_LEVELS   626 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h   uint8_t      PcieLaneCount[NUM_LINK_LEVELS];          ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
NUM_LINK_LEVELS   627 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h   uint16_t     LclkFreq[NUM_LINK_LEVELS];              
NUM_LINK_LEVELS    53 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h #define MAX_LINK_DPM_LEVEL    (NUM_LINK_LEVELS        - 1)
NUM_LINK_LEVELS   236 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h   uint8_t     PcieGenSpeed[NUM_LINK_LEVELS];           /* 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
NUM_LINK_LEVELS   237 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h   uint8_t     PcieLaneCount[NUM_LINK_LEVELS];          /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
NUM_LINK_LEVELS   238 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h   uint8_t     LclkDid[NUM_LINK_LEVELS];                /* Leave at 0 to use hardcoded values in FW */
NUM_LINK_LEVELS    59 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h #define MAX_LINK_LEVEL        (NUM_LINK_LEVELS        - 1)
NUM_LINK_LEVELS   340 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h   uint8_t      PcieGenSpeed[NUM_LINK_LEVELS];
NUM_LINK_LEVELS   341 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h   uint8_t      PcieLaneCount[NUM_LINK_LEVELS];
NUM_LINK_LEVELS   342 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h   uint16_t     LclkFreq[NUM_LINK_LEVELS];
NUM_LINK_LEVELS  1066 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		for (i = 0; i < NUM_LINK_LEVELS; i++)
NUM_LINK_LEVELS  1422 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		if (soft_min_level >= NUM_LINK_LEVELS ||
NUM_LINK_LEVELS  1423 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		    soft_max_level >= NUM_LINK_LEVELS) {