NUMBER_OF_M3ARB_PARAM_SETS  168 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h #ifndef NUMBER_OF_M3ARB_PARAM_SETS
NUMBER_OF_M3ARB_PARAM_SETS  180 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h 	uint32_t          ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];/* arrays with values for CSR M3 arbiter for default */
NUMBER_OF_M3ARB_PARAM_SETS 1690 drivers/gpu/drm/radeon/sumo_dpm.c 		for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) {
NUMBER_OF_M3ARB_PARAM_SETS   91 drivers/gpu/drm/radeon/sumo_dpm.h 	u32 csr_m3_arb_cntl_default[NUMBER_OF_M3ARB_PARAM_SETS];
NUMBER_OF_M3ARB_PARAM_SETS   92 drivers/gpu/drm/radeon/sumo_dpm.h 	u32 csr_m3_arb_cntl_uvd[NUMBER_OF_M3ARB_PARAM_SETS];
NUMBER_OF_M3ARB_PARAM_SETS   93 drivers/gpu/drm/radeon/sumo_dpm.h 	u32 csr_m3_arb_cntl_fs3d[NUMBER_OF_M3ARB_PARAM_SETS];
NUMBER_OF_M3ARB_PARAM_SETS   79 drivers/gpu/drm/radeon/sumo_smc.c 	for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++)
NUMBER_OF_M3ARB_PARAM_SETS   83 drivers/gpu/drm/radeon/sumo_smc.c 	for (; i < NUMBER_OF_M3ARB_PARAM_SETS * 2; i++)
NUMBER_OF_M3ARB_PARAM_SETS   85 drivers/gpu/drm/radeon/sumo_smc.c 			   pi->sys_info.csr_m3_arb_cntl_uvd[i % NUMBER_OF_M3ARB_PARAM_SETS]);
NUMBER_OF_M3ARB_PARAM_SETS   87 drivers/gpu/drm/radeon/sumo_smc.c 	for (; i < NUMBER_OF_M3ARB_PARAM_SETS * 3; i++)
NUMBER_OF_M3ARB_PARAM_SETS   89 drivers/gpu/drm/radeon/sumo_smc.c 			   pi->sys_info.csr_m3_arb_cntl_fs3d[i % NUMBER_OF_M3ARB_PARAM_SETS]);