NR_IRQS_LEGACY 10 arch/arm/include/asm/irq.h #define NR_IRQS NR_IRQS_LEGACY NR_IRQS_LEGACY 41 arch/arm/include/asm/irq.h return NR_IRQS_LEGACY; NR_IRQS_LEGACY 90 arch/arm/mach-imx/mx21.h #define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6) NR_IRQS_LEGACY 91 arch/arm/mach-imx/mx21.h #define MX21_INT_GPIO (NR_IRQS_LEGACY + 8) NR_IRQS_LEGACY 92 arch/arm/mach-imx/mx21.h #define MX21_INT_FIRI (NR_IRQS_LEGACY + 9) NR_IRQS_LEGACY 93 arch/arm/mach-imx/mx21.h #define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10) NR_IRQS_LEGACY 94 arch/arm/mach-imx/mx21.h #define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11) NR_IRQS_LEGACY 95 arch/arm/mach-imx/mx21.h #define MX21_INT_I2C (NR_IRQS_LEGACY + 12) NR_IRQS_LEGACY 96 arch/arm/mach-imx/mx21.h #define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13) NR_IRQS_LEGACY 97 arch/arm/mach-imx/mx21.h #define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14) NR_IRQS_LEGACY 98 arch/arm/mach-imx/mx21.h #define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15) NR_IRQS_LEGACY 99 arch/arm/mach-imx/mx21.h #define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16) NR_IRQS_LEGACY 100 arch/arm/mach-imx/mx21.h #define MX21_INT_UART4 (NR_IRQS_LEGACY + 17) NR_IRQS_LEGACY 101 arch/arm/mach-imx/mx21.h #define MX21_INT_UART3 (NR_IRQS_LEGACY + 18) NR_IRQS_LEGACY 102 arch/arm/mach-imx/mx21.h #define MX21_INT_UART2 (NR_IRQS_LEGACY + 19) NR_IRQS_LEGACY 103 arch/arm/mach-imx/mx21.h #define MX21_INT_UART1 (NR_IRQS_LEGACY + 20) NR_IRQS_LEGACY 104 arch/arm/mach-imx/mx21.h #define MX21_INT_KPP (NR_IRQS_LEGACY + 21) NR_IRQS_LEGACY 105 arch/arm/mach-imx/mx21.h #define MX21_INT_RTC (NR_IRQS_LEGACY + 22) NR_IRQS_LEGACY 106 arch/arm/mach-imx/mx21.h #define MX21_INT_PWM (NR_IRQS_LEGACY + 23) NR_IRQS_LEGACY 107 arch/arm/mach-imx/mx21.h #define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24) NR_IRQS_LEGACY 108 arch/arm/mach-imx/mx21.h #define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25) NR_IRQS_LEGACY 109 arch/arm/mach-imx/mx21.h #define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26) NR_IRQS_LEGACY 110 arch/arm/mach-imx/mx21.h #define MX21_INT_WDOG (NR_IRQS_LEGACY + 27) NR_IRQS_LEGACY 111 arch/arm/mach-imx/mx21.h #define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28) NR_IRQS_LEGACY 112 arch/arm/mach-imx/mx21.h #define MX21_INT_NFC (NR_IRQS_LEGACY + 29) NR_IRQS_LEGACY 113 arch/arm/mach-imx/mx21.h #define MX21_INT_BMI (NR_IRQS_LEGACY + 30) NR_IRQS_LEGACY 114 arch/arm/mach-imx/mx21.h #define MX21_INT_CSI (NR_IRQS_LEGACY + 31) NR_IRQS_LEGACY 115 arch/arm/mach-imx/mx21.h #define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32) NR_IRQS_LEGACY 116 arch/arm/mach-imx/mx21.h #define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33) NR_IRQS_LEGACY 117 arch/arm/mach-imx/mx21.h #define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34) NR_IRQS_LEGACY 118 arch/arm/mach-imx/mx21.h #define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35) NR_IRQS_LEGACY 119 arch/arm/mach-imx/mx21.h #define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36) NR_IRQS_LEGACY 120 arch/arm/mach-imx/mx21.h #define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37) NR_IRQS_LEGACY 121 arch/arm/mach-imx/mx21.h #define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38) NR_IRQS_LEGACY 122 arch/arm/mach-imx/mx21.h #define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39) NR_IRQS_LEGACY 123 arch/arm/mach-imx/mx21.h #define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40) NR_IRQS_LEGACY 124 arch/arm/mach-imx/mx21.h #define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41) NR_IRQS_LEGACY 125 arch/arm/mach-imx/mx21.h #define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42) NR_IRQS_LEGACY 126 arch/arm/mach-imx/mx21.h #define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43) NR_IRQS_LEGACY 127 arch/arm/mach-imx/mx21.h #define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44) NR_IRQS_LEGACY 128 arch/arm/mach-imx/mx21.h #define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45) NR_IRQS_LEGACY 129 arch/arm/mach-imx/mx21.h #define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46) NR_IRQS_LEGACY 130 arch/arm/mach-imx/mx21.h #define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47) NR_IRQS_LEGACY 131 arch/arm/mach-imx/mx21.h #define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49) NR_IRQS_LEGACY 132 arch/arm/mach-imx/mx21.h #define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50) NR_IRQS_LEGACY 133 arch/arm/mach-imx/mx21.h #define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51) NR_IRQS_LEGACY 134 arch/arm/mach-imx/mx21.h #define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52) NR_IRQS_LEGACY 135 arch/arm/mach-imx/mx21.h #define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53) NR_IRQS_LEGACY 136 arch/arm/mach-imx/mx21.h #define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54) NR_IRQS_LEGACY 137 arch/arm/mach-imx/mx21.h #define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55) NR_IRQS_LEGACY 138 arch/arm/mach-imx/mx21.h #define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56) NR_IRQS_LEGACY 139 arch/arm/mach-imx/mx21.h #define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57) NR_IRQS_LEGACY 140 arch/arm/mach-imx/mx21.h #define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58) NR_IRQS_LEGACY 141 arch/arm/mach-imx/mx21.h #define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60) NR_IRQS_LEGACY 142 arch/arm/mach-imx/mx21.h #define MX21_INT_LCDC (NR_IRQS_LEGACY + 61) NR_IRQS_LEGACY 119 arch/arm/mach-imx/mx27.h #define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1) NR_IRQS_LEGACY 120 arch/arm/mach-imx/mx27.h #define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2) NR_IRQS_LEGACY 121 arch/arm/mach-imx/mx27.h #define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3) NR_IRQS_LEGACY 122 arch/arm/mach-imx/mx27.h #define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4) NR_IRQS_LEGACY 123 arch/arm/mach-imx/mx27.h #define MX27_INT_RTIC (NR_IRQS_LEGACY + 5) NR_IRQS_LEGACY 124 arch/arm/mach-imx/mx27.h #define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6) NR_IRQS_LEGACY 125 arch/arm/mach-imx/mx27.h #define MX27_INT_MSHC (NR_IRQS_LEGACY + 7) NR_IRQS_LEGACY 126 arch/arm/mach-imx/mx27.h #define MX27_INT_GPIO (NR_IRQS_LEGACY + 8) NR_IRQS_LEGACY 127 arch/arm/mach-imx/mx27.h #define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9) NR_IRQS_LEGACY 128 arch/arm/mach-imx/mx27.h #define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10) NR_IRQS_LEGACY 129 arch/arm/mach-imx/mx27.h #define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11) NR_IRQS_LEGACY 130 arch/arm/mach-imx/mx27.h #define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12) NR_IRQS_LEGACY 131 arch/arm/mach-imx/mx27.h #define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13) NR_IRQS_LEGACY 132 arch/arm/mach-imx/mx27.h #define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14) NR_IRQS_LEGACY 133 arch/arm/mach-imx/mx27.h #define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15) NR_IRQS_LEGACY 134 arch/arm/mach-imx/mx27.h #define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16) NR_IRQS_LEGACY 135 arch/arm/mach-imx/mx27.h #define MX27_INT_UART4 (NR_IRQS_LEGACY + 17) NR_IRQS_LEGACY 136 arch/arm/mach-imx/mx27.h #define MX27_INT_UART3 (NR_IRQS_LEGACY + 18) NR_IRQS_LEGACY 137 arch/arm/mach-imx/mx27.h #define MX27_INT_UART2 (NR_IRQS_LEGACY + 19) NR_IRQS_LEGACY 138 arch/arm/mach-imx/mx27.h #define MX27_INT_UART1 (NR_IRQS_LEGACY + 20) NR_IRQS_LEGACY 139 arch/arm/mach-imx/mx27.h #define MX27_INT_KPP (NR_IRQS_LEGACY + 21) NR_IRQS_LEGACY 140 arch/arm/mach-imx/mx27.h #define MX27_INT_RTC (NR_IRQS_LEGACY + 22) NR_IRQS_LEGACY 141 arch/arm/mach-imx/mx27.h #define MX27_INT_PWM (NR_IRQS_LEGACY + 23) NR_IRQS_LEGACY 142 arch/arm/mach-imx/mx27.h #define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24) NR_IRQS_LEGACY 143 arch/arm/mach-imx/mx27.h #define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25) NR_IRQS_LEGACY 144 arch/arm/mach-imx/mx27.h #define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26) NR_IRQS_LEGACY 145 arch/arm/mach-imx/mx27.h #define MX27_INT_WDOG (NR_IRQS_LEGACY + 27) NR_IRQS_LEGACY 146 arch/arm/mach-imx/mx27.h #define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28) NR_IRQS_LEGACY 147 arch/arm/mach-imx/mx27.h #define MX27_INT_NFC (NR_IRQS_LEGACY + 29) NR_IRQS_LEGACY 148 arch/arm/mach-imx/mx27.h #define MX27_INT_ATA (NR_IRQS_LEGACY + 30) NR_IRQS_LEGACY 149 arch/arm/mach-imx/mx27.h #define MX27_INT_CSI (NR_IRQS_LEGACY + 31) NR_IRQS_LEGACY 150 arch/arm/mach-imx/mx27.h #define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32) NR_IRQS_LEGACY 151 arch/arm/mach-imx/mx27.h #define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33) NR_IRQS_LEGACY 152 arch/arm/mach-imx/mx27.h #define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34) NR_IRQS_LEGACY 153 arch/arm/mach-imx/mx27.h #define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35) NR_IRQS_LEGACY 154 arch/arm/mach-imx/mx27.h #define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36) NR_IRQS_LEGACY 155 arch/arm/mach-imx/mx27.h #define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37) NR_IRQS_LEGACY 156 arch/arm/mach-imx/mx27.h #define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38) NR_IRQS_LEGACY 157 arch/arm/mach-imx/mx27.h #define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39) NR_IRQS_LEGACY 158 arch/arm/mach-imx/mx27.h #define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40) NR_IRQS_LEGACY 159 arch/arm/mach-imx/mx27.h #define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41) NR_IRQS_LEGACY 160 arch/arm/mach-imx/mx27.h #define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42) NR_IRQS_LEGACY 161 arch/arm/mach-imx/mx27.h #define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43) NR_IRQS_LEGACY 162 arch/arm/mach-imx/mx27.h #define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44) NR_IRQS_LEGACY 163 arch/arm/mach-imx/mx27.h #define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45) NR_IRQS_LEGACY 164 arch/arm/mach-imx/mx27.h #define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46) NR_IRQS_LEGACY 165 arch/arm/mach-imx/mx27.h #define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47) NR_IRQS_LEGACY 166 arch/arm/mach-imx/mx27.h #define MX27_INT_UART6 (NR_IRQS_LEGACY + 48) NR_IRQS_LEGACY 167 arch/arm/mach-imx/mx27.h #define MX27_INT_UART5 (NR_IRQS_LEGACY + 49) NR_IRQS_LEGACY 168 arch/arm/mach-imx/mx27.h #define MX27_INT_FEC (NR_IRQS_LEGACY + 50) NR_IRQS_LEGACY 169 arch/arm/mach-imx/mx27.h #define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51) NR_IRQS_LEGACY 170 arch/arm/mach-imx/mx27.h #define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52) NR_IRQS_LEGACY 171 arch/arm/mach-imx/mx27.h #define MX27_INT_VPU (NR_IRQS_LEGACY + 53) NR_IRQS_LEGACY 172 arch/arm/mach-imx/mx27.h #define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54) NR_IRQS_LEGACY 173 arch/arm/mach-imx/mx27.h #define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55) NR_IRQS_LEGACY 174 arch/arm/mach-imx/mx27.h #define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56) NR_IRQS_LEGACY 175 arch/arm/mach-imx/mx27.h #define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57) NR_IRQS_LEGACY 176 arch/arm/mach-imx/mx27.h #define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58) NR_IRQS_LEGACY 177 arch/arm/mach-imx/mx27.h #define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59) NR_IRQS_LEGACY 178 arch/arm/mach-imx/mx27.h #define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60) NR_IRQS_LEGACY 179 arch/arm/mach-imx/mx27.h #define MX27_INT_LCDC (NR_IRQS_LEGACY + 61) NR_IRQS_LEGACY 180 arch/arm/mach-imx/mx27.h #define MX27_INT_IIM (NR_IRQS_LEGACY + 62) NR_IRQS_LEGACY 181 arch/arm/mach-imx/mx27.h #define MX27_INT_CCM (NR_IRQS_LEGACY + 63) NR_IRQS_LEGACY 59 arch/arm/mach-imx/mx2x.h #define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6) NR_IRQS_LEGACY 60 arch/arm/mach-imx/mx2x.h #define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8) NR_IRQS_LEGACY 61 arch/arm/mach-imx/mx2x.h #define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10) NR_IRQS_LEGACY 62 arch/arm/mach-imx/mx2x.h #define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11) NR_IRQS_LEGACY 63 arch/arm/mach-imx/mx2x.h #define MX2x_INT_I2C (NR_IRQS_LEGACY + 12) NR_IRQS_LEGACY 64 arch/arm/mach-imx/mx2x.h #define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13) NR_IRQS_LEGACY 65 arch/arm/mach-imx/mx2x.h #define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14) NR_IRQS_LEGACY 66 arch/arm/mach-imx/mx2x.h #define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15) NR_IRQS_LEGACY 67 arch/arm/mach-imx/mx2x.h #define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16) NR_IRQS_LEGACY 68 arch/arm/mach-imx/mx2x.h #define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17) NR_IRQS_LEGACY 69 arch/arm/mach-imx/mx2x.h #define MX2x_INT_UART3 (NR_IRQS_LEGACY + 18) NR_IRQS_LEGACY 70 arch/arm/mach-imx/mx2x.h #define MX2x_INT_UART2 (NR_IRQS_LEGACY + 19) NR_IRQS_LEGACY 71 arch/arm/mach-imx/mx2x.h #define MX2x_INT_UART1 (NR_IRQS_LEGACY + 20) NR_IRQS_LEGACY 72 arch/arm/mach-imx/mx2x.h #define MX2x_INT_KPP (NR_IRQS_LEGACY + 21) NR_IRQS_LEGACY 73 arch/arm/mach-imx/mx2x.h #define MX2x_INT_RTC (NR_IRQS_LEGACY + 22) NR_IRQS_LEGACY 74 arch/arm/mach-imx/mx2x.h #define MX2x_INT_PWM (NR_IRQS_LEGACY + 23) NR_IRQS_LEGACY 75 arch/arm/mach-imx/mx2x.h #define MX2x_INT_GPT3 (NR_IRQS_LEGACY + 24) NR_IRQS_LEGACY 76 arch/arm/mach-imx/mx2x.h #define MX2x_INT_GPT2 (NR_IRQS_LEGACY + 25) NR_IRQS_LEGACY 77 arch/arm/mach-imx/mx2x.h #define MX2x_INT_GPT1 (NR_IRQS_LEGACY + 26) NR_IRQS_LEGACY 78 arch/arm/mach-imx/mx2x.h #define MX2x_INT_WDOG (NR_IRQS_LEGACY + 27) NR_IRQS_LEGACY 79 arch/arm/mach-imx/mx2x.h #define MX2x_INT_PCMCIA (NR_IRQS_LEGACY + 28) NR_IRQS_LEGACY 80 arch/arm/mach-imx/mx2x.h #define MX2x_INT_NANDFC (NR_IRQS_LEGACY + 29) NR_IRQS_LEGACY 81 arch/arm/mach-imx/mx2x.h #define MX2x_INT_CSI (NR_IRQS_LEGACY + 31) NR_IRQS_LEGACY 82 arch/arm/mach-imx/mx2x.h #define MX2x_INT_DMACH0 (NR_IRQS_LEGACY + 32) NR_IRQS_LEGACY 83 arch/arm/mach-imx/mx2x.h #define MX2x_INT_DMACH1 (NR_IRQS_LEGACY + 33) NR_IRQS_LEGACY 84 arch/arm/mach-imx/mx2x.h #define MX2x_INT_DMACH2 (NR_IRQS_LEGACY + 34) NR_IRQS_LEGACY 85 arch/arm/mach-imx/mx2x.h #define MX2x_INT_DMACH3 (NR_IRQS_LEGACY + 35) NR_IRQS_LEGACY 86 arch/arm/mach-imx/mx2x.h #define MX2x_INT_DMACH4 (NR_IRQS_LEGACY + 36) NR_IRQS_LEGACY 87 arch/arm/mach-imx/mx2x.h #define MX2x_INT_DMACH5 (NR_IRQS_LEGACY + 37) NR_IRQS_LEGACY 88 arch/arm/mach-imx/mx2x.h #define MX2x_INT_DMACH6 (NR_IRQS_LEGACY + 38) NR_IRQS_LEGACY 89 arch/arm/mach-imx/mx2x.h #define MX2x_INT_DMACH7 (NR_IRQS_LEGACY + 39) NR_IRQS_LEGACY 90 arch/arm/mach-imx/mx2x.h #define MX2x_INT_DMACH8 (NR_IRQS_LEGACY + 40) NR_IRQS_LEGACY 91 arch/arm/mach-imx/mx2x.h #define MX2x_INT_DMACH9 (NR_IRQS_LEGACY + 41) NR_IRQS_LEGACY 92 arch/arm/mach-imx/mx2x.h #define MX2x_INT_DMACH10 (NR_IRQS_LEGACY + 42) NR_IRQS_LEGACY 93 arch/arm/mach-imx/mx2x.h #define MX2x_INT_DMACH11 (NR_IRQS_LEGACY + 43) NR_IRQS_LEGACY 94 arch/arm/mach-imx/mx2x.h #define MX2x_INT_DMACH12 (NR_IRQS_LEGACY + 44) NR_IRQS_LEGACY 95 arch/arm/mach-imx/mx2x.h #define MX2x_INT_DMACH13 (NR_IRQS_LEGACY + 45) NR_IRQS_LEGACY 96 arch/arm/mach-imx/mx2x.h #define MX2x_INT_DMACH14 (NR_IRQS_LEGACY + 46) NR_IRQS_LEGACY 97 arch/arm/mach-imx/mx2x.h #define MX2x_INT_DMACH15 (NR_IRQS_LEGACY + 47) NR_IRQS_LEGACY 98 arch/arm/mach-imx/mx2x.h #define MX2x_INT_EMMAPRP (NR_IRQS_LEGACY + 51) NR_IRQS_LEGACY 99 arch/arm/mach-imx/mx2x.h #define MX2x_INT_EMMAPP (NR_IRQS_LEGACY + 52) NR_IRQS_LEGACY 100 arch/arm/mach-imx/mx2x.h #define MX2x_INT_SLCDC (NR_IRQS_LEGACY + 60) NR_IRQS_LEGACY 101 arch/arm/mach-imx/mx2x.h #define MX2x_INT_LCDC (NR_IRQS_LEGACY + 61) NR_IRQS_LEGACY 126 arch/arm/mach-imx/mx31.h #define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3) NR_IRQS_LEGACY 127 arch/arm/mach-imx/mx31.h #define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4) NR_IRQS_LEGACY 128 arch/arm/mach-imx/mx31.h #define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5) NR_IRQS_LEGACY 129 arch/arm/mach-imx/mx31.h #define MX31_INT_RTIC (NR_IRQS_LEGACY + 6) NR_IRQS_LEGACY 130 arch/arm/mach-imx/mx31.h #define MX31_INT_FIRI (NR_IRQS_LEGACY + 7) NR_IRQS_LEGACY 131 arch/arm/mach-imx/mx31.h #define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8) NR_IRQS_LEGACY 132 arch/arm/mach-imx/mx31.h #define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9) NR_IRQS_LEGACY 133 arch/arm/mach-imx/mx31.h #define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10) NR_IRQS_LEGACY 134 arch/arm/mach-imx/mx31.h #define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11) NR_IRQS_LEGACY 135 arch/arm/mach-imx/mx31.h #define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12) NR_IRQS_LEGACY 136 arch/arm/mach-imx/mx31.h #define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13) NR_IRQS_LEGACY 137 arch/arm/mach-imx/mx31.h #define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14) NR_IRQS_LEGACY 138 arch/arm/mach-imx/mx31.h #define MX31_INT_ATA (NR_IRQS_LEGACY + 15) NR_IRQS_LEGACY 139 arch/arm/mach-imx/mx31.h #define MX31_INT_MBX (NR_IRQS_LEGACY + 16) NR_IRQS_LEGACY 140 arch/arm/mach-imx/mx31.h #define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17) NR_IRQS_LEGACY 141 arch/arm/mach-imx/mx31.h #define MX31_INT_UART3 (NR_IRQS_LEGACY + 18) NR_IRQS_LEGACY 142 arch/arm/mach-imx/mx31.h #define MX31_INT_IIM (NR_IRQS_LEGACY + 19) NR_IRQS_LEGACY 143 arch/arm/mach-imx/mx31.h #define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20) NR_IRQS_LEGACY 144 arch/arm/mach-imx/mx31.h #define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21) NR_IRQS_LEGACY 145 arch/arm/mach-imx/mx31.h #define MX31_INT_RNGA (NR_IRQS_LEGACY + 22) NR_IRQS_LEGACY 146 arch/arm/mach-imx/mx31.h #define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23) NR_IRQS_LEGACY 147 arch/arm/mach-imx/mx31.h #define MX31_INT_KPP (NR_IRQS_LEGACY + 24) NR_IRQS_LEGACY 148 arch/arm/mach-imx/mx31.h #define MX31_INT_RTC (NR_IRQS_LEGACY + 25) NR_IRQS_LEGACY 149 arch/arm/mach-imx/mx31.h #define MX31_INT_PWM (NR_IRQS_LEGACY + 26) NR_IRQS_LEGACY 150 arch/arm/mach-imx/mx31.h #define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27) NR_IRQS_LEGACY 151 arch/arm/mach-imx/mx31.h #define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28) NR_IRQS_LEGACY 152 arch/arm/mach-imx/mx31.h #define MX31_INT_GPT (NR_IRQS_LEGACY + 29) NR_IRQS_LEGACY 153 arch/arm/mach-imx/mx31.h #define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) NR_IRQS_LEGACY 154 arch/arm/mach-imx/mx31.h #define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31) NR_IRQS_LEGACY 155 arch/arm/mach-imx/mx31.h #define MX31_INT_UART2 (NR_IRQS_LEGACY + 32) NR_IRQS_LEGACY 156 arch/arm/mach-imx/mx31.h #define MX31_INT_NFC (NR_IRQS_LEGACY + 33) NR_IRQS_LEGACY 157 arch/arm/mach-imx/mx31.h #define MX31_INT_SDMA (NR_IRQS_LEGACY + 34) NR_IRQS_LEGACY 158 arch/arm/mach-imx/mx31.h #define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35) NR_IRQS_LEGACY 159 arch/arm/mach-imx/mx31.h #define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36) NR_IRQS_LEGACY 160 arch/arm/mach-imx/mx31.h #define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37) NR_IRQS_LEGACY 161 arch/arm/mach-imx/mx31.h #define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39) NR_IRQS_LEGACY 162 arch/arm/mach-imx/mx31.h #define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40) NR_IRQS_LEGACY 163 arch/arm/mach-imx/mx31.h #define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41) NR_IRQS_LEGACY 164 arch/arm/mach-imx/mx31.h #define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42) NR_IRQS_LEGACY 165 arch/arm/mach-imx/mx31.h #define MX31_INT_UART1 (NR_IRQS_LEGACY + 45) NR_IRQS_LEGACY 166 arch/arm/mach-imx/mx31.h #define MX31_INT_UART4 (NR_IRQS_LEGACY + 46) NR_IRQS_LEGACY 167 arch/arm/mach-imx/mx31.h #define MX31_INT_UART5 (NR_IRQS_LEGACY + 47) NR_IRQS_LEGACY 168 arch/arm/mach-imx/mx31.h #define MX31_INT_ECT (NR_IRQS_LEGACY + 48) NR_IRQS_LEGACY 169 arch/arm/mach-imx/mx31.h #define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49) NR_IRQS_LEGACY 170 arch/arm/mach-imx/mx31.h #define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50) NR_IRQS_LEGACY 171 arch/arm/mach-imx/mx31.h #define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51) NR_IRQS_LEGACY 172 arch/arm/mach-imx/mx31.h #define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52) NR_IRQS_LEGACY 173 arch/arm/mach-imx/mx31.h #define MX31_INT_CCM (NR_IRQS_LEGACY + 53) NR_IRQS_LEGACY 174 arch/arm/mach-imx/mx31.h #define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54) NR_IRQS_LEGACY 175 arch/arm/mach-imx/mx31.h #define MX31_INT_WDOG (NR_IRQS_LEGACY + 55) NR_IRQS_LEGACY 176 arch/arm/mach-imx/mx31.h #define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56) NR_IRQS_LEGACY 177 arch/arm/mach-imx/mx31.h #define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58) NR_IRQS_LEGACY 178 arch/arm/mach-imx/mx31.h #define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) NR_IRQS_LEGACY 179 arch/arm/mach-imx/mx31.h #define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) NR_IRQS_LEGACY 180 arch/arm/mach-imx/mx31.h #define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) NR_IRQS_LEGACY 181 arch/arm/mach-imx/mx31.h #define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) NR_IRQS_LEGACY 182 arch/arm/mach-imx/mx31.h #define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63) NR_IRQS_LEGACY 125 arch/arm/mach-imx/mx35.h #define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2) NR_IRQS_LEGACY 126 arch/arm/mach-imx/mx35.h #define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3) NR_IRQS_LEGACY 127 arch/arm/mach-imx/mx35.h #define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4) NR_IRQS_LEGACY 128 arch/arm/mach-imx/mx35.h #define MX35_INT_RTIC (NR_IRQS_LEGACY + 6) NR_IRQS_LEGACY 129 arch/arm/mach-imx/mx35.h #define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7) NR_IRQS_LEGACY 130 arch/arm/mach-imx/mx35.h #define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8) NR_IRQS_LEGACY 131 arch/arm/mach-imx/mx35.h #define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9) NR_IRQS_LEGACY 132 arch/arm/mach-imx/mx35.h #define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10) NR_IRQS_LEGACY 133 arch/arm/mach-imx/mx35.h #define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11) NR_IRQS_LEGACY 134 arch/arm/mach-imx/mx35.h #define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12) NR_IRQS_LEGACY 135 arch/arm/mach-imx/mx35.h #define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13) NR_IRQS_LEGACY 136 arch/arm/mach-imx/mx35.h #define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14) NR_IRQS_LEGACY 137 arch/arm/mach-imx/mx35.h #define MX35_INT_ATA (NR_IRQS_LEGACY + 15) NR_IRQS_LEGACY 138 arch/arm/mach-imx/mx35.h #define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16) NR_IRQS_LEGACY 139 arch/arm/mach-imx/mx35.h #define MX35_INT_ASRC (NR_IRQS_LEGACY + 17) NR_IRQS_LEGACY 140 arch/arm/mach-imx/mx35.h #define MX35_INT_UART3 (NR_IRQS_LEGACY + 18) NR_IRQS_LEGACY 141 arch/arm/mach-imx/mx35.h #define MX35_INT_IIM (NR_IRQS_LEGACY + 19) NR_IRQS_LEGACY 142 arch/arm/mach-imx/mx35.h #define MX35_INT_RNGA (NR_IRQS_LEGACY + 22) NR_IRQS_LEGACY 143 arch/arm/mach-imx/mx35.h #define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23) NR_IRQS_LEGACY 144 arch/arm/mach-imx/mx35.h #define MX35_INT_KPP (NR_IRQS_LEGACY + 24) NR_IRQS_LEGACY 145 arch/arm/mach-imx/mx35.h #define MX35_INT_RTC (NR_IRQS_LEGACY + 25) NR_IRQS_LEGACY 146 arch/arm/mach-imx/mx35.h #define MX35_INT_PWM (NR_IRQS_LEGACY + 26) NR_IRQS_LEGACY 147 arch/arm/mach-imx/mx35.h #define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27) NR_IRQS_LEGACY 148 arch/arm/mach-imx/mx35.h #define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28) NR_IRQS_LEGACY 149 arch/arm/mach-imx/mx35.h #define MX35_INT_GPT (NR_IRQS_LEGACY + 29) NR_IRQS_LEGACY 150 arch/arm/mach-imx/mx35.h #define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) NR_IRQS_LEGACY 151 arch/arm/mach-imx/mx35.h #define MX35_INT_UART2 (NR_IRQS_LEGACY + 32) NR_IRQS_LEGACY 152 arch/arm/mach-imx/mx35.h #define MX35_INT_NFC (NR_IRQS_LEGACY + 33) NR_IRQS_LEGACY 153 arch/arm/mach-imx/mx35.h #define MX35_INT_SDMA (NR_IRQS_LEGACY + 34) NR_IRQS_LEGACY 154 arch/arm/mach-imx/mx35.h #define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35) NR_IRQS_LEGACY 155 arch/arm/mach-imx/mx35.h #define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37) NR_IRQS_LEGACY 156 arch/arm/mach-imx/mx35.h #define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39) NR_IRQS_LEGACY 157 arch/arm/mach-imx/mx35.h #define MX35_INT_ESAI (NR_IRQS_LEGACY + 40) NR_IRQS_LEGACY 158 arch/arm/mach-imx/mx35.h #define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41) NR_IRQS_LEGACY 159 arch/arm/mach-imx/mx35.h #define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42) NR_IRQS_LEGACY 160 arch/arm/mach-imx/mx35.h #define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43) NR_IRQS_LEGACY 161 arch/arm/mach-imx/mx35.h #define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44) NR_IRQS_LEGACY 162 arch/arm/mach-imx/mx35.h #define MX35_INT_UART1 (NR_IRQS_LEGACY + 45) NR_IRQS_LEGACY 163 arch/arm/mach-imx/mx35.h #define MX35_INT_MLB (NR_IRQS_LEGACY + 46) NR_IRQS_LEGACY 164 arch/arm/mach-imx/mx35.h #define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47) NR_IRQS_LEGACY 165 arch/arm/mach-imx/mx35.h #define MX35_INT_ECT (NR_IRQS_LEGACY + 48) NR_IRQS_LEGACY 166 arch/arm/mach-imx/mx35.h #define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49) NR_IRQS_LEGACY 167 arch/arm/mach-imx/mx35.h #define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50) NR_IRQS_LEGACY 168 arch/arm/mach-imx/mx35.h #define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51) NR_IRQS_LEGACY 169 arch/arm/mach-imx/mx35.h #define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52) NR_IRQS_LEGACY 170 arch/arm/mach-imx/mx35.h #define MX35_INT_WDOG (NR_IRQS_LEGACY + 55) NR_IRQS_LEGACY 171 arch/arm/mach-imx/mx35.h #define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56) NR_IRQS_LEGACY 172 arch/arm/mach-imx/mx35.h #define MX35_INT_FEC (NR_IRQS_LEGACY + 57) NR_IRQS_LEGACY 173 arch/arm/mach-imx/mx35.h #define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58) NR_IRQS_LEGACY 174 arch/arm/mach-imx/mx35.h #define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) NR_IRQS_LEGACY 175 arch/arm/mach-imx/mx35.h #define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) NR_IRQS_LEGACY 176 arch/arm/mach-imx/mx35.h #define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) NR_IRQS_LEGACY 177 arch/arm/mach-imx/mx35.h #define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) NR_IRQS_LEGACY 178 arch/arm/mach-imx/mx35.h #define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63) NR_IRQS_LEGACY 143 arch/arm/mach-imx/mx3x.h #define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3) NR_IRQS_LEGACY 144 arch/arm/mach-imx/mx3x.h #define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4) NR_IRQS_LEGACY 145 arch/arm/mach-imx/mx3x.h #define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6) NR_IRQS_LEGACY 146 arch/arm/mach-imx/mx3x.h #define MX3x_INT_I2C (NR_IRQS_LEGACY + 10) NR_IRQS_LEGACY 147 arch/arm/mach-imx/mx3x.h #define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13) NR_IRQS_LEGACY 148 arch/arm/mach-imx/mx3x.h #define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14) NR_IRQS_LEGACY 149 arch/arm/mach-imx/mx3x.h #define MX3x_INT_ATA (NR_IRQS_LEGACY + 15) NR_IRQS_LEGACY 150 arch/arm/mach-imx/mx3x.h #define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18) NR_IRQS_LEGACY 151 arch/arm/mach-imx/mx3x.h #define MX3x_INT_IIM (NR_IRQS_LEGACY + 19) NR_IRQS_LEGACY 152 arch/arm/mach-imx/mx3x.h #define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22) NR_IRQS_LEGACY 153 arch/arm/mach-imx/mx3x.h #define MX3x_INT_EVTMON (NR_IRQS_LEGACY + 23) NR_IRQS_LEGACY 154 arch/arm/mach-imx/mx3x.h #define MX3x_INT_KPP (NR_IRQS_LEGACY + 24) NR_IRQS_LEGACY 155 arch/arm/mach-imx/mx3x.h #define MX3x_INT_RTC (NR_IRQS_LEGACY + 25) NR_IRQS_LEGACY 156 arch/arm/mach-imx/mx3x.h #define MX3x_INT_PWM (NR_IRQS_LEGACY + 26) NR_IRQS_LEGACY 157 arch/arm/mach-imx/mx3x.h #define MX3x_INT_EPIT2 (NR_IRQS_LEGACY + 27) NR_IRQS_LEGACY 158 arch/arm/mach-imx/mx3x.h #define MX3x_INT_EPIT1 (NR_IRQS_LEGACY + 28) NR_IRQS_LEGACY 159 arch/arm/mach-imx/mx3x.h #define MX3x_INT_GPT (NR_IRQS_LEGACY + 29) NR_IRQS_LEGACY 160 arch/arm/mach-imx/mx3x.h #define MX3x_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) NR_IRQS_LEGACY 161 arch/arm/mach-imx/mx3x.h #define MX3x_INT_UART2 (NR_IRQS_LEGACY + 32) NR_IRQS_LEGACY 162 arch/arm/mach-imx/mx3x.h #define MX3x_INT_NANDFC (NR_IRQS_LEGACY + 33) NR_IRQS_LEGACY 163 arch/arm/mach-imx/mx3x.h #define MX3x_INT_SDMA (NR_IRQS_LEGACY + 34) NR_IRQS_LEGACY 164 arch/arm/mach-imx/mx3x.h #define MX3x_INT_MSHC1 (NR_IRQS_LEGACY + 39) NR_IRQS_LEGACY 165 arch/arm/mach-imx/mx3x.h #define MX3x_INT_IPU_ERR (NR_IRQS_LEGACY + 41) NR_IRQS_LEGACY 166 arch/arm/mach-imx/mx3x.h #define MX3x_INT_IPU_SYN (NR_IRQS_LEGACY + 42) NR_IRQS_LEGACY 167 arch/arm/mach-imx/mx3x.h #define MX3x_INT_UART1 (NR_IRQS_LEGACY + 45) NR_IRQS_LEGACY 168 arch/arm/mach-imx/mx3x.h #define MX3x_INT_ECT (NR_IRQS_LEGACY + 48) NR_IRQS_LEGACY 169 arch/arm/mach-imx/mx3x.h #define MX3x_INT_SCC_SCM (NR_IRQS_LEGACY + 49) NR_IRQS_LEGACY 170 arch/arm/mach-imx/mx3x.h #define MX3x_INT_SCC_SMN (NR_IRQS_LEGACY + 50) NR_IRQS_LEGACY 171 arch/arm/mach-imx/mx3x.h #define MX3x_INT_GPIO2 (NR_IRQS_LEGACY + 51) NR_IRQS_LEGACY 172 arch/arm/mach-imx/mx3x.h #define MX3x_INT_GPIO1 (NR_IRQS_LEGACY + 52) NR_IRQS_LEGACY 173 arch/arm/mach-imx/mx3x.h #define MX3x_INT_WDOG (NR_IRQS_LEGACY + 55) NR_IRQS_LEGACY 174 arch/arm/mach-imx/mx3x.h #define MX3x_INT_GPIO3 (NR_IRQS_LEGACY + 56) NR_IRQS_LEGACY 175 arch/arm/mach-imx/mx3x.h #define MX3x_INT_EXT_POWER (NR_IRQS_LEGACY + 58) NR_IRQS_LEGACY 176 arch/arm/mach-imx/mx3x.h #define MX3x_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) NR_IRQS_LEGACY 177 arch/arm/mach-imx/mx3x.h #define MX3x_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) NR_IRQS_LEGACY 178 arch/arm/mach-imx/mx3x.h #define MX3x_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) NR_IRQS_LEGACY 179 arch/arm/mach-imx/mx3x.h #define MX3x_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) NR_IRQS_LEGACY 180 arch/arm/mach-imx/mx3x.h #define MX3x_INT_EXT_TV (NR_IRQS_LEGACY + 63) NR_IRQS_LEGACY 157 arch/arm/mach-omap1/ams-delta-fiq.c ((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4; NR_IRQS_LEGACY 197 arch/arm/mach-omap1/ams-delta-fiq.c offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4; NR_IRQS_LEGACY 24 arch/arm/mach-omap1/include/mach/irqs.h #define INT_CAMERA (NR_IRQS_LEGACY + 1) NR_IRQS_LEGACY 25 arch/arm/mach-omap1/include/mach/irqs.h #define INT_FIQ (NR_IRQS_LEGACY + 3) NR_IRQS_LEGACY 26 arch/arm/mach-omap1/include/mach/irqs.h #define INT_RTDX (NR_IRQS_LEGACY + 6) NR_IRQS_LEGACY 27 arch/arm/mach-omap1/include/mach/irqs.h #define INT_DSP_MMU_ABORT (NR_IRQS_LEGACY + 7) NR_IRQS_LEGACY 28 arch/arm/mach-omap1/include/mach/irqs.h #define INT_HOST (NR_IRQS_LEGACY + 8) NR_IRQS_LEGACY 29 arch/arm/mach-omap1/include/mach/irqs.h #define INT_ABORT (NR_IRQS_LEGACY + 9) NR_IRQS_LEGACY 30 arch/arm/mach-omap1/include/mach/irqs.h #define INT_BRIDGE_PRIV (NR_IRQS_LEGACY + 13) NR_IRQS_LEGACY 31 arch/arm/mach-omap1/include/mach/irqs.h #define INT_GPIO_BANK1 (NR_IRQS_LEGACY + 14) NR_IRQS_LEGACY 32 arch/arm/mach-omap1/include/mach/irqs.h #define INT_UART3 (NR_IRQS_LEGACY + 15) NR_IRQS_LEGACY 33 arch/arm/mach-omap1/include/mach/irqs.h #define INT_TIMER3 (NR_IRQS_LEGACY + 16) NR_IRQS_LEGACY 34 arch/arm/mach-omap1/include/mach/irqs.h #define INT_DMA_CH0_6 (NR_IRQS_LEGACY + 19) NR_IRQS_LEGACY 35 arch/arm/mach-omap1/include/mach/irqs.h #define INT_DMA_CH1_7 (NR_IRQS_LEGACY + 20) NR_IRQS_LEGACY 36 arch/arm/mach-omap1/include/mach/irqs.h #define INT_DMA_CH2_8 (NR_IRQS_LEGACY + 21) NR_IRQS_LEGACY 37 arch/arm/mach-omap1/include/mach/irqs.h #define INT_DMA_CH3 (NR_IRQS_LEGACY + 22) NR_IRQS_LEGACY 38 arch/arm/mach-omap1/include/mach/irqs.h #define INT_DMA_CH4 (NR_IRQS_LEGACY + 23) NR_IRQS_LEGACY 39 arch/arm/mach-omap1/include/mach/irqs.h #define INT_DMA_CH5 (NR_IRQS_LEGACY + 24) NR_IRQS_LEGACY 40 arch/arm/mach-omap1/include/mach/irqs.h #define INT_TIMER1 (NR_IRQS_LEGACY + 26) NR_IRQS_LEGACY 41 arch/arm/mach-omap1/include/mach/irqs.h #define INT_WD_TIMER (NR_IRQS_LEGACY + 27) NR_IRQS_LEGACY 42 arch/arm/mach-omap1/include/mach/irqs.h #define INT_BRIDGE_PUB (NR_IRQS_LEGACY + 28) NR_IRQS_LEGACY 43 arch/arm/mach-omap1/include/mach/irqs.h #define INT_TIMER2 (NR_IRQS_LEGACY + 30) NR_IRQS_LEGACY 44 arch/arm/mach-omap1/include/mach/irqs.h #define INT_LCD_CTRL (NR_IRQS_LEGACY + 31) NR_IRQS_LEGACY 49 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1510_IH2_IRQ (NR_IRQS_LEGACY + 0) NR_IRQS_LEGACY 50 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1510_RES2 (NR_IRQS_LEGACY + 2) NR_IRQS_LEGACY 51 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1510_SPI_TX (NR_IRQS_LEGACY + 4) NR_IRQS_LEGACY 52 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1510_SPI_RX (NR_IRQS_LEGACY + 5) NR_IRQS_LEGACY 53 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1510_DSP_MAILBOX1 (NR_IRQS_LEGACY + 10) NR_IRQS_LEGACY 54 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1510_DSP_MAILBOX2 (NR_IRQS_LEGACY + 11) NR_IRQS_LEGACY 55 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1510_RES12 (NR_IRQS_LEGACY + 12) NR_IRQS_LEGACY 56 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1510_LB_MMU (NR_IRQS_LEGACY + 17) NR_IRQS_LEGACY 57 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1510_RES18 (NR_IRQS_LEGACY + 18) NR_IRQS_LEGACY 58 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1510_LOCAL_BUS (NR_IRQS_LEGACY + 29) NR_IRQS_LEGACY 64 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1610_IH2_FIQ (NR_IRQS_LEGACY + 2) NR_IRQS_LEGACY 65 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1610_McBSP2_TX (NR_IRQS_LEGACY + 4) NR_IRQS_LEGACY 66 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1610_McBSP2_RX (NR_IRQS_LEGACY + 5) NR_IRQS_LEGACY 67 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1610_DSP_MAILBOX1 (NR_IRQS_LEGACY + 10) NR_IRQS_LEGACY 68 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1610_DSP_MAILBOX2 (NR_IRQS_LEGACY + 11) NR_IRQS_LEGACY 69 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1610_LCD_LINE (NR_IRQS_LEGACY + 12) NR_IRQS_LEGACY 70 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1610_GPTIMER1 (NR_IRQS_LEGACY + 17) NR_IRQS_LEGACY 71 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1610_GPTIMER2 (NR_IRQS_LEGACY + 18) NR_IRQS_LEGACY 72 arch/arm/mach-omap1/include/mach/irqs.h #define INT_1610_SSR_FIFO_0 (NR_IRQS_LEGACY + 29) NR_IRQS_LEGACY 77 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_IH2_FIQ (NR_IRQS_LEGACY + 0) NR_IRQS_LEGACY 78 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_IH2_IRQ (NR_IRQS_LEGACY + 1) NR_IRQS_LEGACY 79 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_USB_NON_ISO (NR_IRQS_LEGACY + 2) NR_IRQS_LEGACY 80 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_USB_ISO (NR_IRQS_LEGACY + 3) NR_IRQS_LEGACY 81 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_ICR (NR_IRQS_LEGACY + 4) NR_IRQS_LEGACY 82 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_EAC (NR_IRQS_LEGACY + 5) NR_IRQS_LEGACY 83 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_GPIO_BANK1 (NR_IRQS_LEGACY + 6) NR_IRQS_LEGACY 84 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_GPIO_BANK2 (NR_IRQS_LEGACY + 7) NR_IRQS_LEGACY 85 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_GPIO_BANK3 (NR_IRQS_LEGACY + 8) NR_IRQS_LEGACY 86 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_McBSP2TX (NR_IRQS_LEGACY + 10) NR_IRQS_LEGACY 87 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_McBSP2RX (NR_IRQS_LEGACY + 11) NR_IRQS_LEGACY 88 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_McBSP2RX_OVF (NR_IRQS_LEGACY + 12) NR_IRQS_LEGACY 89 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_LCD_LINE (NR_IRQS_LEGACY + 14) NR_IRQS_LEGACY 90 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_GSM_PROTECT (NR_IRQS_LEGACY + 15) NR_IRQS_LEGACY 91 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_TIMER3 (NR_IRQS_LEGACY + 16) NR_IRQS_LEGACY 92 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_GPIO_BANK5 (NR_IRQS_LEGACY + 17) NR_IRQS_LEGACY 93 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_GPIO_BANK6 (NR_IRQS_LEGACY + 18) NR_IRQS_LEGACY 94 arch/arm/mach-omap1/include/mach/irqs.h #define INT_7XX_SPGIO_WR (NR_IRQS_LEGACY + 29) NR_IRQS_LEGACY 101 arch/arm/mach-omap1/include/mach/irqs.h #define IH2_BASE (NR_IRQS_LEGACY + 32) NR_IRQS_LEGACY 245 arch/arm/mach-omap1/include/mach/irqs.h #define OMAP_IRQ_BIT(irq) (1 << ((irq - NR_IRQS_LEGACY) % 32)) NR_IRQS_LEGACY 236 arch/arm/mach-omap1/irq.c omap_l2_irq -= NR_IRQS_LEGACY; NR_IRQS_LEGACY 15 arch/arm/mach-pxa/include/mach/irqs.h #define PXA_IRQ(x) (NR_IRQS_LEGACY + (x)) NR_IRQS_LEGACY 147 arch/x86/include/asm/io_apic.h #define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs)) NR_IRQS_LEGACY 207 arch/x86/include/asm/io_apic.h #define gsi_top (NR_IRQS_LEGACY) NR_IRQS_LEGACY 143 arch/x86/include/asm/irq_vectors.h #define NR_IRQS NR_IRQS_LEGACY NR_IRQS_LEGACY 97 arch/x86/kernel/acpi/boot.c static u32 isa_irq_to_gsi[NR_IRQS_LEGACY] __read_mostly = { NR_IRQS_LEGACY 345 arch/x86/kernel/acpi/boot.c if (bus_irq >= NR_IRQS_LEGACY) { NR_IRQS_LEGACY 478 arch/x86/kernel/acpi/boot.c if (bus_irq < NR_IRQS_LEGACY) NR_IRQS_LEGACY 652 arch/x86/kernel/apic/vector.c if (gsi_top <= NR_IRQS_LEGACY) NR_IRQS_LEGACY 411 arch/x86/kernel/i8259.c .nr_legacy_irqs = NR_IRQS_LEGACY, NR_IRQS_LEGACY 488 arch/x86/pci/xen.c for (irq = 0; irq < NR_IRQS_LEGACY; irq++) { NR_IRQS_LEGACY 20 drivers/clk/imx/clk-imx1.c #define MX1_TIM1_INT (NR_IRQS_LEGACY + 59) NR_IRQS_LEGACY 21 drivers/clk/imx/clk-imx21.c #define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26) NR_IRQS_LEGACY 18 drivers/clk/imx/clk-imx27.c #define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26) NR_IRQS_LEGACY 21 drivers/clk/imx/clk-imx31.c #define MX31_INT_GPT (NR_IRQS_LEGACY + 29) NR_IRQS_LEGACY 20 drivers/clk/imx/clk-imx35.c #define MX35_INT_GPT (NR_IRQS_LEGACY + 29) NR_IRQS_LEGACY 552 include/linux/irq.h #ifndef NR_IRQS_LEGACY NR_IRQS_LEGACY 19 include/linux/omap-dma.h #define INT_DMA_LCD (NR_IRQS_LEGACY + 25) NR_IRQS_LEGACY 702 kernel/softirq.c return NR_IRQS_LEGACY;