AARCH64_DBG_REG_BCR 89 arch/arm64/include/asm/hw_breakpoint.h #define AARCH64_DBG_REG_WVR (AARCH64_DBG_REG_BCR + ARM_MAX_BRP) AARCH64_DBG_REG_BCR 111 arch/arm64/kernel/hw_breakpoint.c GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val); AARCH64_DBG_REG_BCR 126 arch/arm64/kernel/hw_breakpoint.c GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val); AARCH64_DBG_REG_BCR 234 arch/arm64/kernel/hw_breakpoint.c ctrl_reg = AARCH64_DBG_REG_BCR; AARCH64_DBG_REG_BCR 587 arch/arm64/kernel/hw_breakpoint.c case AARCH64_DBG_REG_BCR: AARCH64_DBG_REG_BCR 648 arch/arm64/kernel/hw_breakpoint.c ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i); AARCH64_DBG_REG_BCR 668 arch/arm64/kernel/hw_breakpoint.c toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 0); AARCH64_DBG_REG_BCR 679 arch/arm64/kernel/hw_breakpoint.c toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 0); AARCH64_DBG_REG_BCR 858 arch/arm64/kernel/hw_breakpoint.c toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 1); AARCH64_DBG_REG_BCR 878 arch/arm64/kernel/hw_breakpoint.c toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 1); AARCH64_DBG_REG_BCR 919 arch/arm64/kernel/hw_breakpoint.c toggle_bp_registers(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_BCR 951 arch/arm64/kernel/hw_breakpoint.c write_wb_reg(AARCH64_DBG_REG_BCR, i, 0UL);