NBIO_BASE          39 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c 		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
NBIO_BASE          39 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
NBIO_BASE          39 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
NBIO_BASE          50 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 		adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
NBIO_BASE         446 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX),
NBIO_BASE         447 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
NBIO_BASE         190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) +  \
NBIO_BASE         451 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
NBIO_BASE         314 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
NBIO_BASE          97 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE NBIO_BASE            ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } },
NBIO_BASE          43 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE NBIO_BASE			= { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
NBIO_BASE          99 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE NBIO_BASE            ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } },