NAND_CMD_READSTART 1001 drivers/mtd/nand/raw/atmel/nand-controller.c 		nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
NAND_CMD_READSTART  113 drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c 		ctlcode |= NAND_CMD_READSTART << 8;
NAND_CMD_READSTART  245 drivers/mtd/nand/raw/cafe_nand.c 		cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
NAND_CMD_READSTART  291 drivers/mtd/nand/raw/fsl_elbc_nand.c 		                    (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
NAND_CMD_READSTART  269 drivers/mtd/nand/raw/fsl_ifc_nand.c 			  (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
NAND_CMD_READSTART  264 drivers/mtd/nand/raw/hisi504_nand.c 	hinfc_write(host, NAND_CMD_READSTART << 8 | NAND_CMD_READ0,
NAND_CMD_READSTART  995 drivers/mtd/nand/raw/marvell_nand.c 			   NDCB0_CMD2(NAND_CMD_READSTART),
NAND_CMD_READSTART 1263 drivers/mtd/nand/raw/marvell_nand.c 				  NDCB0_CMD2(NAND_CMD_READSTART);
NAND_CMD_READSTART  616 drivers/mtd/nand/raw/meson_nand.c 		nfc->cmdfifo.rw.cmd1 = cs | NFC_CMD_CLE | NAND_CMD_READSTART;
NAND_CMD_READSTART  374 drivers/mtd/nand/raw/mpc5121_nfc.c 			mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
NAND_CMD_READSTART  728 drivers/mtd/nand/raw/mxc_nand.c 		host->devtype_data->send_cmd(host, NAND_CMD_READSTART, true);
NAND_CMD_READSTART  788 drivers/mtd/nand/raw/mxc_nand.c 				NAND_CMD_READSTART, true);
NAND_CMD_READSTART 1065 drivers/mtd/nand/raw/nand_base.c 		NAND_OP_CMD(NAND_CMD_READSTART, PSEC_TO_NSEC(sdr->tWB_max)),
NAND_CMD_READSTART  482 drivers/mtd/nand/raw/nand_legacy.c 		chip->legacy.cmd_ctrl(chip, NAND_CMD_READSTART,
NAND_CMD_READSTART 1070 drivers/mtd/nand/raw/nandsim.c 	case NAND_CMD_READSTART:
NAND_CMD_READSTART 1100 drivers/mtd/nand/raw/nandsim.c 		case NAND_CMD_READSTART:
NAND_CMD_READSTART  629 drivers/mtd/nand/raw/sh_flctl.c 		(NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
NAND_CMD_READSTART  676 drivers/mtd/nand/raw/sh_flctl.c 		(NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
NAND_CMD_READSTART  760 drivers/mtd/nand/raw/sh_flctl.c 			set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
NAND_CMD_READSTART  781 drivers/mtd/nand/raw/sh_flctl.c 			set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
NAND_CMD_READSTART  819 drivers/mtd/nand/raw/stm32_fmc2_nand.c 			    FMC2_CSQCFGR1_CMD2(NAND_CMD_READSTART) |
NAND_CMD_READSTART  930 drivers/mtd/nand/raw/sunxi_nand.c 	       NAND_CMD_READSTART, nfc->regs + NFC_REG_RCMD_SET);
NAND_CMD_READSTART  505 drivers/mtd/nand/raw/tegra_nand.c 		writel_relaxed(NAND_CMD_READSTART, ctrl->regs + CMD_REG2);
NAND_CMD_READSTART  567 drivers/mtd/nand/raw/vf610_nfc.c 	cmd1 |= NAND_CMD_READSTART << CMD_BYTE2_SHIFT;