N2                 34 drivers/clk/pxa/clk-pxa25x.c #define PXA25x_CCCR(N2, M, L) (N2 << 7 | M << 5 | L)
N2                 51 drivers/clk/pxa/clk-pxa27x.c #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
N2                161 drivers/gpu/drm/nouveau/dispnv04/crtc.c 			 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
N2                140 drivers/gpu/drm/nouveau/dispnv04/hw.c 	pllvals->N2 = pllvals->M2 = 1;
N2                155 drivers/gpu/drm/nouveau/dispnv04/hw.c 				pllvals->N2 = ((pll1 >> 21) & 0x18) |
N2                210 drivers/gpu/drm/nouveau/dispnv04/hw.c 	return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;
N2                  9 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h 			uint8_t N1, M1, N2, M2;
N2                 11 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h 			uint8_t M1, N1, M2, N2;
N2                 35 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c 	int N1, M1, N2, M2, P;
N2                 36 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c 	int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P);
N2                 41 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c 		pv->N2 = N2;
N2                 61 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 	int N2 = (coef & 0xff000000) >> 24;
N2                 72 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 				khz = khz * N2 / M2;
N2                125 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 		  int *N1, int *M1, int *N2, int *M2, int *log2P)
N2                138 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 	ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P);
N2                151 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 	int N1, M1, N2, M2, log2P;
N2                156 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 				&N1, &M1, &N2, &M2, &log2P);
N2                160 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 	if (N2 == M2) {
N2                165 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 		clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
N2                166 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	int N1, N2, M1, M2;
N2                174 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	N2 = (coef & 0xff000000) >> 24;
N2                182 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 				freq = freq * N2 / M2;
N2                  9 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h 		  int *N1, int *M1, int *N2, int *M2, int *P);
N2                151 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 	int M1, N1, M2, N2, log2P;
N2                184 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 				N2 = (clkP * M2 + calcclk1/2) / calcclk1;
N2                185 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 				if (N2 < minN2)
N2                187 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 				if (N2 > maxN2)
N2                192 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 						if (N2/M2 < 4 || N2/M2 > 10)
N2                195 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 					calcclk2 = calcclk1 * N2 / M2;
N2                213 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 					*pN2 = N2;
N2                228 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 	      int *N1, int *M1, int *N2, int *M2, int *P)
N2                232 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 	if (!info->vco2.max_freq || !N2) {
N2                234 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 		if (N2) {
N2                235 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 			*N2 = 1;
N2                239 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 		ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P);
N2                210 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c 	bool single_stage = !pv->NM2 || pv->N2 == pv->M2;	/* nv41+ only */
N2                216 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c 		pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
N2                217 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c 		       (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
N2                296 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c 	bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
N2                363 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c 	int N1, M1, N2, M2, P;
N2                370 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c 	ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
N2                377 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c 	pv.N2 = N2;
N2                 41 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c 	int N1, M1, N2, M2, P;
N2                 50 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c 	ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
N2                 62 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c 							    (M2 << 16) | N2);
N2                134 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 	int N2, M2, P2;
N2                160 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 	const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2);
N2                990 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 		int *N2, int *M2, int *P2)
N2               1013 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 				*N2 = cur_N;
N2               1024 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 				*N2 = cur_N;
N2               1033 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 	*fN1 = (u16)((((best_err / *N2 * *P2) * (*P1 * *M1)) << 13) / crystal);
N2               1067 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 				&ram->N2, &ram->M2, &ram->P2);
N2                 40 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c 	int N1, M1, N2, M2;
N2                 49 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c 	ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P);
N2                 55 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c 	if (N2 == M2) {
N2                 60 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c 		ram->coef  = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
N2                231 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	int N1, M1, N2, M2, P;
N2                332 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 				    &N1, &M1, &N2, &M2, &P);
N2               2058 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c 	u16 N1, N2, N3, N4, N5, N6, N;
N2               2061 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c 	N2 = 1 << ((read_phy_reg(pi, 0x4a5) & (0x7 << 12))
N2               2071 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c 	N = 2 * (N1 + N2 + N3 + N4 + 2 * (N5 + N6)) + 80;
N2               1544 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c SIG_EXPR_LIST_DECL_SINGLE(N2, GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
N2               1545 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c SIG_EXPR_LIST_DECL_SINGLE(N2, ADC13, ADC13);
N2               1546 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c PIN_DECL_(N2, SIG_EXPR_LIST_PTR(N2, GPIOX5), SIG_EXPR_LIST_PTR(N2, ADC13));
N2               1547 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c FUNC_GROUP_DECL(ADC13, N2);
N2               2070 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c 	ASPEED_PINCTRL_PIN(N2),
N2               2518 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c 	{ PIN_CONFIG_BIAS_PULL_DOWN, { N2,  N2  }, SCUA8, 17 },
N2               2519 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c 	{ PIN_CONFIG_BIAS_DISABLE,   { N2,  N2  }, SCUA8, 17 },
N2                662 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c SIG_EXPR_LIST_DECL_SINGLE(N2, SDA6, I2C6, I2C6_DESC);
N2                663 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c PIN_DECL_1(N2, GPIOK3, SDA6);
N2                665 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c FUNC_GROUP_DECL(I2C6, L1, N2);
N2               2059 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c 	ASPEED_PINCTRL_PIN(N2),
N2               2213 drivers/tty/n_gsm.c 	gsm->n2 = N2;