N1                161 drivers/gpu/drm/nouveau/dispnv04/crtc.c 			 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
N1                164 drivers/gpu/drm/nouveau/dispnv04/crtc.c 			 pv->N1, pv->M1, pv->log2P);
N1                210 drivers/gpu/drm/nouveau/dispnv04/hw.c 	return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;
N1                271 drivers/gpu/drm/nouveau/dispnv04/hw.c 	    pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n &&
N1                279 drivers/gpu/drm/nouveau/dispnv04/hw.c 	pv.N1 = pll_lim.vco1.min_n;
N1                  9 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h 			uint8_t N1, M1, N2, M2;
N1                 11 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h 			uint8_t M1, N1, M2, N2;
N1                 57 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 	int N1, M1;
N1                 70 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 	N1 = (coef & 0x0000ff00) >> 8;
N1                 73 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 		clock = ref * N1 / M1;
N1                 35 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c 	int N1, M1, N2, M2, P;
N1                 36 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c 	int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P);
N1                 39 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c 		pv->N1 = N1;
N1                 63 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 	int N1 = (coef & 0x0000ff00) >> 8;
N1                 69 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 		khz = ref * N1 / M1;
N1                125 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 		  int *N1, int *M1, int *N2, int *M2, int *log2P)
N1                138 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 	ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P);
N1                151 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 	int N1, M1, N2, M2, log2P;
N1                156 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 				&N1, &M1, &N2, &M2, &log2P);
N1                162 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 		clk->npll_coef = (N1 << 8) | M1;
N1                165 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 		clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
N1                171 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 					&N1, &M1, NULL, NULL, &log2P);
N1                175 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 		clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;
N1                166 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	int N1, N2, M1, M2;
N1                176 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	N1 = (coef & 0x0000ff00) >> 8;
N1                179 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		freq = ref * N1 / M1;
N1                  9 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h 		  int *N1, int *M1, int *N2, int *M2, int *P);
N1                151 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 	int M1, N1, M2, N2, log2P;
N1                170 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 		for (N1 = minN1; N1 <= maxN1; N1++) {
N1                171 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 			calcclk1 = crystal * N1 / M1;
N1                211 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 					*pN1 = N1;
N1                228 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 	      int *N1, int *M1, int *N2, int *M2, int *P)
N1                233 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 		ret = getMNP_single(subdev, info, freq, N1, M1, P);
N1                239 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 		ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P);
N1                164 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c 	if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
N1                363 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c 	int N1, M1, N2, M2, P;
N1                370 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c 	ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
N1                375 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c 	pv.N1 = N1;
N1                 41 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c 	int N1, M1, N2, M2, P;
N1                 50 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c 	ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
N1                 60 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c 		nvkm_mask(device, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1);
N1                 69 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c 		nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1);
N1                 73 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c 		nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1);
N1                143 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c 	int N1, M1, P;
N1                216 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c 				     &N1, NULL, &M1, &P);
N1                225 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c 		ram_wr32(fuc, 0x10fe24, (P << 16) | (N1 << 8) | M1);
N1                231 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c 				     &N1, NULL, &M1, &P);
N1                238 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c 		ram_wr32(fuc, 0x132004, (P << 16) | (N1 << 8) | M1);
N1                133 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 	int N1, fN1, M1, P1;
N1                161 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 	const u32 rcoef = ((  ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
N1                703 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 	const u32 rcoef = ((  ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
N1                989 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 		int *N1, int *fN1, int *M1, int *P1,
N1               1014 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 				*N1 = n_ref;
N1               1025 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 				*N1 = n_ref;
N1               1037 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 	return gk104_calc_pll_output(*fN1, 1, *N1, *P1, crystal);
N1               1066 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 				&ram->N1, &ram->fN1, &ram->M1, &ram->P1,
N1               1077 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 		ret = gt215_pll_calc(subdev, &fuc->refpll, refclk, &ram->N1,
N1                 40 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c 	int N1, M1, N2, M2;
N1                 49 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c 	ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P);
N1                 57 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c 		ram->coef  = (N1 << 8) | M1;
N1                 60 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c 		ram->coef  = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
N1                231 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	int N1, M1, N2, M2, P;
N1                332 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 				    &N1, &M1, &N2, &M2, &P);
N1                356 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1);
N1               2058 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c 	u16 N1, N2, N3, N4, N5, N6, N;
N1               2059 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c 	N1 = ((read_phy_reg(pi, 0x4a5) & (0xff << 0))
N1               2071 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c 	N = 2 * (N1 + N2 + N3 + N4 + 2 * (N5 + N6)) + 80;
N1               1550 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c SIG_EXPR_LIST_DECL_SINGLE(N1, GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
N1               1551 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c SIG_EXPR_LIST_DECL_SINGLE(N1, ADC14, ADC14);
N1               1552 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c PIN_DECL_(N1, SIG_EXPR_LIST_PTR(N1, GPIOX6), SIG_EXPR_LIST_PTR(N1, ADC14));
N1               1553 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c FUNC_GROUP_DECL(ADC14, N1);
N1               2067 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c 	ASPEED_PINCTRL_PIN(N1),
N1               2520 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c 	{ PIN_CONFIG_BIAS_PULL_DOWN, { N1,  N1  }, SCUA8, 18 },
N1               2521 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c 	{ PIN_CONFIG_BIAS_DISABLE,   { N1,  N1  }, SCUA8, 18 },
N1                670 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c SIG_EXPR_LIST_DECL_SINGLE(N1, SCL7, I2C7, I2C7_DESC);
N1                671 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c PIN_DECL_1(N1, GPIOK4, SCL7);
N1                677 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c FUNC_GROUP_DECL(I2C7, N1, P1);
N1               2056 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c 	ASPEED_PINCTRL_PIN(N1),