MX_CLKSEL2_PLL_2x_VAL   61 arch/arm/mach-omap2/opp2420_data.c 		MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
MX_CLKSEL2_PLL_2x_VAL   68 arch/arm/mach-omap2/opp2420_data.c 		MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
MX_CLKSEL2_PLL_2x_VAL   74 arch/arm/mach-omap2/opp2420_data.c 		MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
MX_CLKSEL2_PLL_2x_VAL   81 arch/arm/mach-omap2/opp2420_data.c 		MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
MX_CLKSEL2_PLL_2x_VAL   87 arch/arm/mach-omap2/opp2420_data.c 		MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
MX_CLKSEL2_PLL_2x_VAL   94 arch/arm/mach-omap2/opp2420_data.c 		MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
MX_CLKSEL2_PLL_2x_VAL  100 arch/arm/mach-omap2/opp2420_data.c 		MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
MX_CLKSEL2_PLL_2x_VAL  107 arch/arm/mach-omap2/opp2420_data.c 		MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
MX_CLKSEL2_PLL_2x_VAL  113 arch/arm/mach-omap2/opp2420_data.c 		MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
MX_CLKSEL2_PLL_2x_VAL  120 arch/arm/mach-omap2/opp2420_data.c 		MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
MX_CLKSEL2_PLL_2x_VAL  127 arch/arm/mach-omap2/opp2420_data.c 		MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
MX_CLKSEL2_PLL_2x_VAL   59 arch/arm/mach-omap2/opp2430_data.c 		MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
MX_CLKSEL2_PLL_2x_VAL   67 arch/arm/mach-omap2/opp2430_data.c 		MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
MX_CLKSEL2_PLL_2x_VAL   75 arch/arm/mach-omap2/opp2430_data.c 		MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
MX_CLKSEL2_PLL_2x_VAL   83 arch/arm/mach-omap2/opp2430_data.c 		MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
MX_CLKSEL2_PLL_2x_VAL  123 arch/arm/mach-omap2/opp2430_data.c 		MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
MX_CLKSEL2_PLL_2x_VAL  131 arch/arm/mach-omap2/opp2430_data.c 		MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,