AST_IO_CRTC_PORT   21 drivers/gpu/drm/ast/ast_dp501.c 	sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
AST_IO_CRTC_PORT   23 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
AST_IO_CRTC_PORT   29 drivers/gpu/drm/ast/ast_dp501.c 	sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
AST_IO_CRTC_PORT   31 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
AST_IO_CRTC_PORT   39 drivers/gpu/drm/ast/ast_dp501.c 		waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
AST_IO_CRTC_PORT   55 drivers/gpu/drm/ast/ast_dp501.c 		waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
AST_IO_CRTC_PORT   68 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40);
AST_IO_CRTC_PORT   73 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00);
AST_IO_CRTC_PORT   82 drivers/gpu/drm/ast/ast_dp501.c 		waitready = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
AST_IO_CRTC_PORT  100 drivers/gpu/drm/ast/ast_dp501.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
AST_IO_CRTC_PORT  122 drivers/gpu/drm/ast/ast_dp501.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
AST_IO_CRTC_PORT  143 drivers/gpu/drm/ast/ast_dp501.c 	tmp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd3, 0xff);
AST_IO_CRTC_PORT  156 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, 0x00);
AST_IO_CRTC_PORT  249 drivers/gpu/drm/ast/ast_dp501.c 		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */
AST_IO_CRTC_PORT  251 drivers/gpu/drm/ast/ast_dp501.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x99, jreg);
AST_IO_CRTC_PORT  322 drivers/gpu/drm/ast/ast_dp501.c 	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
AST_IO_CRTC_PORT  381 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);
AST_IO_CRTC_PORT  410 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x00);
AST_IO_CRTC_PORT  419 drivers/gpu/drm/ast/ast_dp501.c 		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
AST_IO_CRTC_PORT  191 drivers/gpu/drm/ast/ast_drv.h 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8);
AST_IO_CRTC_PORT   96 drivers/gpu/drm/ast/ast_main.c 	jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
AST_IO_CRTC_PORT   97 drivers/gpu/drm/ast/ast_main.c 	jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
AST_IO_CRTC_PORT  194 drivers/gpu/drm/ast/ast_main.c 		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
AST_IO_CRTC_PORT  226 drivers/gpu/drm/ast/ast_main.c 		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
AST_IO_CRTC_PORT  237 drivers/gpu/drm/ast/ast_main.c 		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
AST_IO_CRTC_PORT  403 drivers/gpu/drm/ast/ast_main.c 	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff);
AST_IO_CRTC_PORT  411 drivers/gpu/drm/ast/ast_main.c 	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff);
AST_IO_CRTC_PORT  526 drivers/gpu/drm/ast/ast_main.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04);
AST_IO_CRTC_PORT  212 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4));
AST_IO_CRTC_PORT  213 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
AST_IO_CRTC_PORT  214 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
AST_IO_CRTC_PORT  216 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
AST_IO_CRTC_PORT  218 drivers/gpu/drm/ast/ast_mode.c 			ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
AST_IO_CRTC_PORT  219 drivers/gpu/drm/ast/ast_mode.c 			ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92,
AST_IO_CRTC_PORT  221 drivers/gpu/drm/ast/ast_mode.c 			ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
AST_IO_CRTC_PORT  222 drivers/gpu/drm/ast/ast_mode.c 			ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
AST_IO_CRTC_PORT  223 drivers/gpu/drm/ast/ast_mode.c 			ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
AST_IO_CRTC_PORT  225 drivers/gpu/drm/ast/ast_mode.c 			ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
AST_IO_CRTC_PORT  226 drivers/gpu/drm/ast/ast_mode.c 			ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
AST_IO_CRTC_PORT  257 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
AST_IO_CRTC_PORT  259 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
AST_IO_CRTC_PORT  290 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
AST_IO_CRTC_PORT  295 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
AST_IO_CRTC_PORT  300 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
AST_IO_CRTC_PORT  305 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
AST_IO_CRTC_PORT  312 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
AST_IO_CRTC_PORT  317 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
AST_IO_CRTC_PORT  322 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
AST_IO_CRTC_PORT  324 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
AST_IO_CRTC_PORT  325 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
AST_IO_CRTC_PORT  335 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
AST_IO_CRTC_PORT  344 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
AST_IO_CRTC_PORT  351 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
AST_IO_CRTC_PORT  360 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
AST_IO_CRTC_PORT  369 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
AST_IO_CRTC_PORT  374 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
AST_IO_CRTC_PORT  376 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
AST_IO_CRTC_PORT  377 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
AST_IO_CRTC_PORT  378 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
AST_IO_CRTC_PORT  381 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
AST_IO_CRTC_PORT  383 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
AST_IO_CRTC_PORT  385 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
AST_IO_CRTC_PORT  396 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
AST_IO_CRTC_PORT  397 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
AST_IO_CRTC_PORT  411 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
AST_IO_CRTC_PORT  412 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
AST_IO_CRTC_PORT  413 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
AST_IO_CRTC_PORT  444 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
AST_IO_CRTC_PORT  445 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
AST_IO_CRTC_PORT  446 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
AST_IO_CRTC_PORT  451 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
AST_IO_CRTC_PORT  452 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
AST_IO_CRTC_PORT  457 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
AST_IO_CRTC_PORT  458 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
AST_IO_CRTC_PORT  460 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
AST_IO_CRTC_PORT  461 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
AST_IO_CRTC_PORT  498 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
AST_IO_CRTC_PORT  499 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
AST_IO_CRTC_PORT  500 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
AST_IO_CRTC_PORT  588 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
AST_IO_CRTC_PORT  807 drivers/gpu/drm/ast/ast_mode.c 				jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
AST_IO_CRTC_PORT  966 drivers/gpu/drm/ast/ast_mode.c 	val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
AST_IO_CRTC_PORT  968 drivers/gpu/drm/ast/ast_mode.c 		val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
AST_IO_CRTC_PORT  973 drivers/gpu/drm/ast/ast_mode.c 			val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
AST_IO_CRTC_PORT  988 drivers/gpu/drm/ast/ast_mode.c 	val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
AST_IO_CRTC_PORT  990 drivers/gpu/drm/ast/ast_mode.c 		val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
AST_IO_CRTC_PORT  995 drivers/gpu/drm/ast/ast_mode.c 			val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
AST_IO_CRTC_PORT 1011 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7);
AST_IO_CRTC_PORT 1012 drivers/gpu/drm/ast/ast_mode.c 		jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
AST_IO_CRTC_PORT 1027 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7);
AST_IO_CRTC_PORT 1028 drivers/gpu/drm/ast/ast_mode.c 		jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
AST_IO_CRTC_PORT 1087 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
AST_IO_CRTC_PORT 1093 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00);
AST_IO_CRTC_PORT 1225 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff);
AST_IO_CRTC_PORT 1226 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff);
AST_IO_CRTC_PORT 1227 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff);
AST_IO_CRTC_PORT 1276 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
AST_IO_CRTC_PORT 1277 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
AST_IO_CRTC_PORT 1278 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff));
AST_IO_CRTC_PORT 1279 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f));
AST_IO_CRTC_PORT 1280 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff));
AST_IO_CRTC_PORT 1281 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07));
AST_IO_CRTC_PORT   52 drivers/gpu/drm/ast/ast_post.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
AST_IO_CRTC_PORT   83 drivers/gpu/drm/ast/ast_post.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
AST_IO_CRTC_PORT   96 drivers/gpu/drm/ast/ast_post.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info);
AST_IO_CRTC_PORT  105 drivers/gpu/drm/ast/ast_post.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01);
AST_IO_CRTC_PORT  106 drivers/gpu/drm/ast/ast_post.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00);
AST_IO_CRTC_PORT  113 drivers/gpu/drm/ast/ast_post.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
AST_IO_CRTC_PORT  284 drivers/gpu/drm/ast/ast_post.c 	j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
AST_IO_CRTC_PORT  366 drivers/gpu/drm/ast/ast_post.c 		j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
AST_IO_CRTC_PORT  395 drivers/gpu/drm/ast/ast_post.c 			ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);	/* Enable DVO */
AST_IO_CRTC_PORT 1608 drivers/gpu/drm/ast/ast_post.c 	reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
AST_IO_CRTC_PORT 1680 drivers/gpu/drm/ast/ast_post.c 		reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
AST_IO_CRTC_PORT 2039 drivers/gpu/drm/ast/ast_post.c 	reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
AST_IO_CRTC_PORT 2082 drivers/gpu/drm/ast/ast_post.c 		reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);