MX31_IO_ADDRESS 38 arch/arm/mach-imx/cpu-imx31.c srev = imx_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV)); MX31_IO_ADDRESS 34 arch/arm/mach-imx/ehci-imx31.c v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); MX31_IO_ADDRESS 71 arch/arm/mach-imx/ehci-imx31.c writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); MX31_IO_ADDRESS 19 arch/arm/mach-imx/iomux-imx31.c #define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR) MX31_IO_ADDRESS 38 arch/arm/mach-imx/mach-kzm_arm11_01.c MX31_IO_ADDRESS(x)) MX31_IO_ADDRESS 491 arch/arm/mach-imx/mach-mx31moboard.c imx_writew(1 << 6 | 1 << 2, MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); MX31_IO_ADDRESS 183 arch/arm/mach-imx/mach-qong.c imx_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3))); MX31_IO_ADDRESS 184 arch/arm/mach-imx/mach-qong.c imx_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3))); MX31_IO_ADDRESS 185 arch/arm/mach-imx/mach-qong.c imx_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3))); MX31_IO_ADDRESS 142 arch/arm/mach-imx/mm-imx3.c mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); MX31_IO_ADDRESS 147 arch/arm/mach-imx/mm-imx3.c mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); MX31_IO_ADDRESS 179 arch/arm/mach-imx/mm-imx3.c mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); MX31_IO_ADDRESS 196 arch/arm/mach-imx/mm-imx3.c imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR)); MX31_IO_ADDRESS 197 arch/arm/mach-imx/mm-imx3.c imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));