MSTPCR2 42 arch/sh/boot/romimage/mmcif-sh7724.c __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2); MSTPCR2 75 arch/sh/boot/romimage/mmcif-sh7724.c __raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2); MSTPCR2 166 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0), MSTPCR2 167 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0), MSTPCR2 168 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0), MSTPCR2 169 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0), MSTPCR2 170 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0), MSTPCR2 171 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0), MSTPCR2 172 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0), MSTPCR2 173 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0), MSTPCR2 174 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0), MSTPCR2 175 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0), MSTPCR2 176 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), MSTPCR2 177 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0), MSTPCR2 178 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0), MSTPCR2 179 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0), MSTPCR2 180 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), MSTPCR2 181 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), MSTPCR2 182 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0), MSTPCR2 166 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0), MSTPCR2 167 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0), MSTPCR2 168 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0), MSTPCR2 169 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0), MSTPCR2 170 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0), MSTPCR2 171 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0), MSTPCR2 172 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0), MSTPCR2 173 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0), MSTPCR2 174 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT), MSTPCR2 175 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0), MSTPCR2 176 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0), MSTPCR2 177 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0), MSTPCR2 178 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), MSTPCR2 179 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), MSTPCR2 180 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0), MSTPCR2 155 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_SDHI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 18, 0), MSTPCR2 156 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0), MSTPCR2 157 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_USBF] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 11, 0), MSTPCR2 158 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0), MSTPCR2 159 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0), MSTPCR2 160 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), MSTPCR2 161 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), MSTPCR2 162 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), MSTPCR2 163 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), MSTPCR2 164 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_VEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), MSTPCR2 165 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), MSTPCR2 166 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 0, 0), MSTPCR2 173 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0), MSTPCR2 174 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_ADC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 27, 0), MSTPCR2 175 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0), MSTPCR2 176 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0), MSTPCR2 177 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0), MSTPCR2 178 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_ICB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, CLK_ENABLE_ON_INIT), MSTPCR2 179 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0), MSTPCR2 180 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0), MSTPCR2 181 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0), MSTPCR2 182 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_USB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 11, 0), MSTPCR2 183 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 10, 0), MSTPCR2 184 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0), MSTPCR2 185 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_VEU2H1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), MSTPCR2 186 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), MSTPCR2 187 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), MSTPCR2 188 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), MSTPCR2 189 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_VEU2H0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), MSTPCR2 190 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), MSTPCR2 191 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0), MSTPCR2 234 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 29, 0), MSTPCR2 235 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 28, 0), MSTPCR2 236 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 26, 0), MSTPCR2 237 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0), MSTPCR2 238 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0), MSTPCR2 239 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0), MSTPCR2 240 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_USB1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, 0), MSTPCR2 241 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_USB0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 20, 0), MSTPCR2 242 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 19, 0), MSTPCR2 243 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0), MSTPCR2 244 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0), MSTPCR2 245 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_VEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 15, 0), MSTPCR2 246 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_CEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 13, 0), MSTPCR2 247 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_BEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 12, 0), MSTPCR2 248 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0), MSTPCR2 249 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0), MSTPCR2 250 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), MSTPCR2 251 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), MSTPCR2 252 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), MSTPCR2 253 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), MSTPCR2 254 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), MSTPCR2 255 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), MSTPCR2 256 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0), MSTPCR2 99 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),