MSTPCR0 139 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), MSTPCR0 140 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), MSTPCR0 141 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), MSTPCR0 142 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), MSTPCR0 143 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), MSTPCR0 144 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), MSTPCR0 145 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), MSTPCR0 146 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), MSTPCR0 147 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0), MSTPCR0 148 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0), MSTPCR0 149 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0), MSTPCR0 150 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0), MSTPCR0 151 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0), MSTPCR0 152 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0), MSTPCR0 153 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0), MSTPCR0 154 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0), MSTPCR0 155 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0), MSTPCR0 156 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0), MSTPCR0 157 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0), MSTPCR0 158 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0), MSTPCR0 159 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0), MSTPCR0 160 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0), MSTPCR0 161 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0), MSTPCR0 142 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), MSTPCR0 143 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), MSTPCR0 144 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), MSTPCR0 145 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), MSTPCR0 146 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), MSTPCR0 147 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), MSTPCR0 148 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), MSTPCR0 149 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), MSTPCR0 150 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0), MSTPCR0 151 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0), MSTPCR0 152 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0), MSTPCR0 153 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0), MSTPCR0 154 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0), MSTPCR0 155 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0), MSTPCR0 156 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0), MSTPCR0 157 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0), MSTPCR0 158 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0), MSTPCR0 159 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0), MSTPCR0 160 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0), MSTPCR0 161 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0), MSTPCR0 162 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0), MSTPCR0 142 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), MSTPCR0 143 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), MSTPCR0 144 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_TMU] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), MSTPCR0 145 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0), MSTPCR0 146 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0), MSTPCR0 147 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), MSTPCR0 148 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), MSTPCR0 149 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0), MSTPCR0 150 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0), MSTPCR0 143 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), MSTPCR0 144 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), MSTPCR0 145 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), MSTPCR0 146 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), MSTPCR0 147 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT), MSTPCR0 148 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT), MSTPCR0 149 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 22, CLK_ENABLE_ON_INIT), MSTPCR0 150 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0), MSTPCR0 151 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT), MSTPCR0 152 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0), MSTPCR0 153 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0), MSTPCR0 154 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), MSTPCR0 155 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0), MSTPCR0 156 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0), MSTPCR0 157 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0), MSTPCR0 158 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0), MSTPCR0 159 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), MSTPCR0 160 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), MSTPCR0 161 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), MSTPCR0 162 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), MSTPCR0 163 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0), MSTPCR0 164 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0), MSTPCR0 165 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0), MSTPCR0 166 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0), MSTPCR0 167 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0), MSTPCR0 168 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_MERAM] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 0, 0), MSTPCR0 203 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), MSTPCR0 204 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), MSTPCR0 205 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), MSTPCR0 206 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT), MSTPCR0 207 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT), MSTPCR0 208 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT), MSTPCR0 209 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT), MSTPCR0 210 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT), MSTPCR0 211 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0), MSTPCR0 212 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT), MSTPCR0 213 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0), MSTPCR0 214 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0), MSTPCR0 215 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), MSTPCR0 216 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0), MSTPCR0 217 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0), MSTPCR0 218 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0), MSTPCR0 219 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), MSTPCR0 220 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), MSTPCR0 221 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), MSTPCR0 222 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), MSTPCR0 223 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0), MSTPCR0 224 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0), MSTPCR0 225 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0), MSTPCR0 226 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0), MSTPCR0 227 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0), MSTPCR0 126 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), MSTPCR0 127 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), MSTPCR0 128 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), MSTPCR0 129 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), MSTPCR0 130 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), MSTPCR0 131 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), MSTPCR0 132 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), MSTPCR0 133 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), MSTPCR0 134 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP019] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0), MSTPCR0 135 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), MSTPCR0 136 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), MSTPCR0 137 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), MSTPCR0 138 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0), MSTPCR0 139 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0), MSTPCR0 140 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), MSTPCR0 141 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), MSTPCR0 142 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), MSTPCR0 143 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), MSTPCR0 85 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0), MSTPCR0 86 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0), MSTPCR0 91 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), MSTPCR0 92 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), MSTPCR0 93 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), MSTPCR0 94 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), MSTPCR0 95 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), MSTPCR0 96 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), MSTPCR0 97 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), MSTPCR0 98 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0), MSTPCR0 99 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0), MSTPCR0 100 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), MSTPCR0 101 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0), MSTPCR0 102 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0), MSTPCR0 103 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), MSTPCR0 104 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), MSTPCR0 105 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0), MSTPCR0 106 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), MSTPCR0 92 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), MSTPCR0 93 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), MSTPCR0 94 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), MSTPCR0 95 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), MSTPCR0 96 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), MSTPCR0 97 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), MSTPCR0 98 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), MSTPCR0 99 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), MSTPCR0 100 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), MSTPCR0 101 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0), MSTPCR0 102 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0), MSTPCR0 103 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), MSTPCR0 104 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), MSTPCR0 105 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), MSTPCR0 106 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0), MSTPCR0 107 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), MSTPCR0 108 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), MSTPCR0 109 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), MSTPCR0 110 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0), MSTPCR0 111 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0), MSTPCR0 112 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), MSTPCR0 83 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), MSTPCR0 84 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), MSTPCR0 85 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), MSTPCR0 86 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), MSTPCR0 87 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), MSTPCR0 88 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), MSTPCR0 89 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0), MSTPCR0 90 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), MSTPCR0 91 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0), MSTPCR0 92 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),