MSR_P6_EVNTSEL0 143 arch/x86/events/intel/p6.c rdmsrl(MSR_P6_EVNTSEL0, val); MSR_P6_EVNTSEL0 145 arch/x86/events/intel/p6.c wrmsrl(MSR_P6_EVNTSEL0, val); MSR_P6_EVNTSEL0 153 arch/x86/events/intel/p6.c rdmsrl(MSR_P6_EVNTSEL0, val); MSR_P6_EVNTSEL0 155 arch/x86/events/intel/p6.c wrmsrl(MSR_P6_EVNTSEL0, val); MSR_P6_EVNTSEL0 210 arch/x86/events/intel/p6.c .eventsel = MSR_P6_EVNTSEL0, MSR_P6_EVNTSEL0 89 arch/x86/kernel/cpu/perfctr-watchdog.c return msr - MSR_P6_EVNTSEL0; MSR_P6_EVNTSEL0 108 arch/x86/kvm/vmx/pmu_intel.c return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + pmc_idx, MSR_P6_EVNTSEL0 109 arch/x86/kvm/vmx/pmu_intel.c MSR_P6_EVNTSEL0); MSR_P6_EVNTSEL0 165 arch/x86/kvm/vmx/pmu_intel.c get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) || MSR_P6_EVNTSEL0 200 arch/x86/kvm/vmx/pmu_intel.c } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) { MSR_P6_EVNTSEL0 257 arch/x86/kvm/vmx/pmu_intel.c } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) { MSR_P6_EVNTSEL0 2872 arch/x86/kvm/x86.c case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: MSR_P6_EVNTSEL0 3017 arch/x86/kvm/x86.c case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: MSR_P6_EVNTSEL0 41 arch/x86/oprofile/op_model_ppro.c release_evntsel_nmi(MSR_P6_EVNTSEL0 + i); MSR_P6_EVNTSEL0 52 arch/x86/oprofile/op_model_ppro.c if (!reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i)) { MSR_P6_EVNTSEL0 58 arch/x86/oprofile/op_model_ppro.c msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i; MSR_P6_EVNTSEL0 170 arch/x86/xen/pmu.c if ((msr_index >= MSR_P6_EVNTSEL0) && MSR_P6_EVNTSEL0 171 arch/x86/xen/pmu.c (msr_index < MSR_P6_EVNTSEL0 + intel_num_arch_counters)) { MSR_P6_EVNTSEL0 172 arch/x86/xen/pmu.c *index = msr_index - MSR_P6_EVNTSEL0;