MSR_P4_TC_ESCR0 74 arch/x86/events/intel/p4.c .escr_msr = { MSR_P4_TC_ESCR0, MSR_P4_TC_ESCR1 }, MSR_P4_TC_ESCR0 317 arch/x86/events/intel/p4.c .escr_msr = { MSR_P4_TC_ESCR0, MSR_P4_TC_ESCR1 }, MSR_P4_TC_ESCR0 1172 arch/x86/events/intel/p4.c P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TC_ESCR0), MSR_P4_TC_ESCR0 123 arch/x86/oprofile/op_model_p4.c { { CTR_MS_0, MSR_P4_TC_ESCR0},