MSR_P4_TBPU_ESCR1  357 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_TBPU_ESCR0 , MSR_P4_TBPU_ESCR1 },
MSR_P4_TBPU_ESCR1 1171 arch/x86/events/intel/p4.c 	P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TBPU_ESCR1),
MSR_P4_TBPU_ESCR1  334 arch/x86/oprofile/op_model_p4.c 		  { CTR_MS_2, MSR_P4_TBPU_ESCR1} }
MSR_P4_TBPU_ESCR1  340 arch/x86/oprofile/op_model_p4.c 		  { CTR_MS_2, MSR_P4_TBPU_ESCR1} }