MSR_P4_FSB_ESCR1  168 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
MSR_P4_FSB_ESCR1  185 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_FSB_ESCR1,  MSR_P4_FSB_ESCR1 },
MSR_P4_FSB_ESCR1  202 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
MSR_P4_FSB_ESCR1  324 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
MSR_P4_FSB_ESCR1  383 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
MSR_P4_FSB_ESCR1  389 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
MSR_P4_FSB_ESCR1  395 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
MSR_P4_FSB_ESCR1  401 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
MSR_P4_FSB_ESCR1 1149 arch/x86/events/intel/p4.c 	P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FSB_ESCR1),
MSR_P4_FSB_ESCR1  189 arch/x86/oprofile/op_model_p4.c 		{ { CTR_BPU_2, MSR_P4_FSB_ESCR1},
MSR_P4_FSB_ESCR1  196 arch/x86/oprofile/op_model_p4.c 		  { CTR_BPU_2, MSR_P4_FSB_ESCR1} }
MSR_P4_FSB_ESCR1  280 arch/x86/oprofile/op_model_p4.c 		  { CTR_BPU_2, MSR_P4_FSB_ESCR1} }