MSR_P4_FSB_ESCR0  168 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
MSR_P4_FSB_ESCR0  202 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
MSR_P4_FSB_ESCR0  324 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
MSR_P4_FSB_ESCR0  383 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
MSR_P4_FSB_ESCR0  389 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
MSR_P4_FSB_ESCR0  395 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
MSR_P4_FSB_ESCR0  401 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
MSR_P4_FSB_ESCR0 1148 arch/x86/events/intel/p4.c 	P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FSB_ESCR0),
MSR_P4_FSB_ESCR0  183 arch/x86/oprofile/op_model_p4.c 		{ { CTR_BPU_0, MSR_P4_FSB_ESCR0},
MSR_P4_FSB_ESCR0  195 arch/x86/oprofile/op_model_p4.c 		{ { CTR_BPU_0, MSR_P4_FSB_ESCR0},
MSR_P4_FSB_ESCR0  279 arch/x86/oprofile/op_model_p4.c 		{ { CTR_BPU_0, MSR_P4_FSB_ESCR0},