MSR_P4_CRU_ESCR2 407 arch/x86/events/intel/p4.c .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 }, MSR_P4_CRU_ESCR2 415 arch/x86/events/intel/p4.c .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 }, MSR_P4_CRU_ESCR2 429 arch/x86/events/intel/p4.c .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 }, MSR_P4_CRU_ESCR2 463 arch/x86/events/intel/p4.c .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 }, MSR_P4_CRU_ESCR2 480 arch/x86/events/intel/p4.c .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 }, MSR_P4_CRU_ESCR2 491 arch/x86/events/intel/p4.c .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 }, MSR_P4_CRU_ESCR2 1138 arch/x86/events/intel/p4.c P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR2), MSR_P4_CRU_ESCR2 111 arch/x86/oprofile/op_model_p4.c { {CTR_IQ_4, MSR_P4_CRU_ESCR2}, MSR_P4_CRU_ESCR2 213 arch/x86/oprofile/op_model_p4.c { { CTR_IQ_4, MSR_P4_CRU_ESCR2}, MSR_P4_CRU_ESCR2 273 arch/x86/oprofile/op_model_p4.c { { CTR_IQ_4, MSR_P4_CRU_ESCR2}, MSR_P4_CRU_ESCR2 297 arch/x86/oprofile/op_model_p4.c { { CTR_IQ_4, MSR_P4_CRU_ESCR2}, MSR_P4_CRU_ESCR2 303 arch/x86/oprofile/op_model_p4.c { { CTR_IQ_4, MSR_P4_CRU_ESCR2}, MSR_P4_CRU_ESCR2 309 arch/x86/oprofile/op_model_p4.c { { CTR_IQ_4, MSR_P4_CRU_ESCR2},