MSR_P4_CRU_ESCR1  437 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
MSR_P4_CRU_ESCR1  447 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
MSR_P4_CRU_ESCR1  473 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
MSR_P4_CRU_ESCR1  500 arch/x86/events/intel/p4.c 		.escr_msr	= { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
MSR_P4_CRU_ESCR1 1137 arch/x86/events/intel/p4.c 	P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR1),
MSR_P4_CRU_ESCR1  118 arch/x86/oprofile/op_model_p4.c 		  { CTR_IQ_5, MSR_P4_CRU_ESCR1} }
MSR_P4_CRU_ESCR1  316 arch/x86/oprofile/op_model_p4.c 		  { CTR_IQ_5, MSR_P4_CRU_ESCR1} }
MSR_P4_CRU_ESCR1  322 arch/x86/oprofile/op_model_p4.c 		  { CTR_IQ_5, MSR_P4_CRU_ESCR1} }