MSR_OFFCORE_RSP_1  166 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
MSR_OFFCORE_RSP_1  212 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
MSR_OFFCORE_RSP_1  219 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
MSR_OFFCORE_RSP_1  227 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
MSR_OFFCORE_RSP_1  234 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
MSR_OFFCORE_RSP_1  267 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
MSR_OFFCORE_RSP_1 1463 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
MSR_OFFCORE_RSP_1 1616 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
MSR_OFFCORE_RSP_1 1896 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
MSR_OFFCORE_RSP_1 2628 arch/x86/events/intel/core.c 		event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;