MSR_OFFCORE_RSP_0   90 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
MSR_OFFCORE_RSP_0  165 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
MSR_OFFCORE_RSP_0  211 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
MSR_OFFCORE_RSP_0  218 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
MSR_OFFCORE_RSP_0  226 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
MSR_OFFCORE_RSP_0  233 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
MSR_OFFCORE_RSP_0  266 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
MSR_OFFCORE_RSP_0 1462 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
MSR_OFFCORE_RSP_0 1615 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
MSR_OFFCORE_RSP_0 1895 arch/x86/events/intel/core.c 	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
MSR_OFFCORE_RSP_0 2624 arch/x86/events/intel/core.c 		event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;