MSR_K7_EVNTSEL0   910 arch/x86/events/amd/core.c 	.eventsel		= MSR_K7_EVNTSEL0,
MSR_K7_EVNTSEL0    82 arch/x86/kernel/cpu/perfctr-watchdog.c 		return msr - MSR_K7_EVNTSEL0;
MSR_K7_EVNTSEL0    60 arch/x86/kvm/pmu_amd.c 			return MSR_K7_EVNTSEL0;
MSR_K7_EVNTSEL0    69 arch/x86/kvm/pmu_amd.c 	case MSR_K7_EVNTSEL0:
MSR_K7_EVNTSEL0   108 arch/x86/kvm/pmu_amd.c 	case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
MSR_K7_EVNTSEL0  2871 arch/x86/kvm/x86.c 	case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
MSR_K7_EVNTSEL0  3014 arch/x86/kvm/x86.c 	case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
MSR_K7_EVNTSEL0   298 arch/x86/oprofile/op_model_amd.c 		release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
MSR_K7_EVNTSEL0   309 arch/x86/oprofile/op_model_amd.c 		if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {
MSR_K7_EVNTSEL0   318 arch/x86/oprofile/op_model_amd.c 			msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
MSR_K7_EVNTSEL0    89 arch/x86/xen/pmu.c 			amd_ctrls_base = MSR_K7_EVNTSEL0;
MSR_K7_EVNTSEL0    97 arch/x86/xen/pmu.c 		amd_ctrls_base = MSR_K7_EVNTSEL0;
MSR_K7_EVNTSEL0   120 arch/x86/xen/pmu.c 	case MSR_K7_EVNTSEL0:
MSR_K7_EVNTSEL0   124 arch/x86/xen/pmu.c 		return MSR_F15H_PERF_CTL + (addr - MSR_K7_EVNTSEL0);
MSR_K7_EVNTSEL0   136 arch/x86/xen/pmu.c 	    (msr >= MSR_K7_EVNTSEL0 &&
MSR_K7_EVNTSEL0   265 arch/x86/xen/pmu.c 	    ((msr >= MSR_K7_EVNTSEL0) && (msr <= MSR_K7_PERFCTR3)))