MSR_IR 138 arch/powerpc/include/asm/reg.h #define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV) MSR_IR 151 arch/powerpc/include/asm/reg.h #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR) MSR_IR 46 arch/powerpc/include/asm/reg_booke.h #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE) MSR_IR 52 arch/powerpc/kernel/head_32.h li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR) /* can take exceptions */ MSR_IR 82 arch/powerpc/kernel/head_32.h LOAD_REG_IMMEDIATE(r10, MSR_KERNEL & ~(MSR_IR|MSR_DR)) /* can take exceptions */ MSR_IR 267 arch/powerpc/kernel/kprobes.c if (!(regs->msr & MSR_IR) || !(regs->msr & MSR_DR)) MSR_IR 192 arch/powerpc/kernel/paca.c new_paca->kernel_msr = MSR_KERNEL & ~(MSR_IR | MSR_DR); MSR_IR 1235 arch/powerpc/kernel/process.c if (!(regs->msr & MSR_IR)) MSR_IR 1322 arch/powerpc/kernel/process.c {MSR_IR, "IR"}, MSR_IR 1492 arch/powerpc/kernel/traps.c if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) MSR_IR 457 arch/powerpc/kvm/book3s.c int relocated = (kvmppc_get_msr(vcpu) & (data ? MSR_DR : MSR_IR)); MSR_IR 471 arch/powerpc/kvm/book3s.c if ((kvmppc_get_msr(vcpu) & (MSR_IR | MSR_DR)) == MSR_DR && MSR_IR 361 arch/powerpc/kvm/book3s_32_mmu.c if (msr & (MSR_DR|MSR_IR)) { MSR_IR 370 arch/powerpc/kvm/book3s_32_mmu.c switch (msr & (MSR_DR|MSR_IR)) { MSR_IR 374 arch/powerpc/kvm/book3s_32_mmu.c case MSR_IR: MSR_IR 380 arch/powerpc/kvm/book3s_32_mmu.c case MSR_DR|MSR_IR: MSR_IR 498 arch/powerpc/kvm/book3s_64_mmu.c if (kvmppc_get_msr(vcpu) & MSR_IR) { MSR_IR 597 arch/powerpc/kvm/book3s_64_mmu.c if (msr & (MSR_DR|MSR_IR)) { MSR_IR 610 arch/powerpc/kvm/book3s_64_mmu.c switch (msr & (MSR_DR|MSR_IR)) { MSR_IR 614 arch/powerpc/kvm/book3s_64_mmu.c case MSR_IR: MSR_IR 620 arch/powerpc/kvm/book3s_64_mmu.c case MSR_DR|MSR_IR: MSR_IR 350 arch/powerpc/kvm/book3s_64_mmu_hv.c int virtmode = vcpu->arch.shregs.msr & (data ? MSR_DR : MSR_IR); MSR_IR 211 arch/powerpc/kvm/book3s_hv_builtin.c if (kvm_is_radix(vcpu->kvm) && (mfmsr() & MSR_IR)) MSR_IR 1312 arch/powerpc/kvm/book3s_hv_rm_mmu.c if (data && (vcpu->arch.shregs.msr & MSR_IR)) MSR_IR 69 arch/powerpc/kvm/book3s_pr.c return (msr & (MSR_IR|MSR_DR)) == MSR_DR; MSR_IR 78 arch/powerpc/kvm/book3s_pr.c if ((msr & (MSR_IR|MSR_DR)) != MSR_DR) MSR_IR 201 arch/powerpc/kvm/book3s_pr.c smsr |= MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_PR | MSR_EE; MSR_IR 495 arch/powerpc/kvm/book3s_pr.c if ((kvmppc_get_msr(vcpu) & (MSR_PR|MSR_IR|MSR_DR)) != MSR_IR 496 arch/powerpc/kvm/book3s_pr.c (old_msr & (MSR_PR|MSR_IR|MSR_DR))) { MSR_IR 677 arch/powerpc/kvm/book3s_pr.c bool ir = (kvmppc_get_msr(vcpu) & MSR_IR) ? true : false; MSR_IR 698 arch/powerpc/kvm/book3s_pr.c switch (kvmppc_get_msr(vcpu) & (MSR_DR|MSR_IR)) { MSR_IR 708 arch/powerpc/kvm/book3s_pr.c case MSR_IR: MSR_IR 711 arch/powerpc/kvm/book3s_pr.c if ((kvmppc_get_msr(vcpu) & (MSR_DR|MSR_IR)) == MSR_DR) MSR_IR 27 arch/powerpc/platforms/82xx/pq2.c mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR)); MSR_IR 389 arch/powerpc/platforms/powernv/idle.c WARN_ON_ONCE(mfmsr() & (MSR_IR|MSR_DR)); MSR_IR 700 arch/powerpc/platforms/powernv/idle.c WARN_ON_ONCE(mfmsr() & (MSR_IR|MSR_DR)); MSR_IR 100 arch/powerpc/platforms/powernv/opal-call.c bool mmu = (msr & (MSR_IR|MSR_DR)); MSR_IR 476 arch/powerpc/platforms/pseries/ras.c (MSR_LE|MSR_RI|MSR_DR|MSR_IR|MSR_ME|MSR_PR| MSR_IR 696 arch/powerpc/platforms/pseries/ras.c mtmsr(mfmsr() | MSR_IR | MSR_DR); MSR_IR 551 arch/powerpc/xmon/xmon.c if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) == (MSR_IR|MSR_64BIT)) MSR_IR 705 arch/powerpc/xmon/xmon.c if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) == (MSR_IR|MSR_64BIT)) { MSR_IR 758 arch/powerpc/xmon/xmon.c if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) != (MSR_IR|MSR_64BIT)) MSR_IR 789 arch/powerpc/xmon/xmon.c if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) != (MSR_IR|MSR_64BIT)) MSR_IR 799 arch/powerpc/xmon/xmon.c if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) != (MSR_IR|MSR_64BIT)) MSR_IR 824 arch/powerpc/xmon/xmon.c if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) == (MSR_IR|MSR_64BIT)) { MSR_IR 1175 arch/powerpc/xmon/xmon.c if ((regs->msr & (MSR_64BIT|MSR_PR|MSR_IR)) == (MSR_64BIT|MSR_IR)) {