MSR_IA32_APICBASE_ENABLE 1278 arch/x86/kernel/apic/apic.c l &= ~MSR_IA32_APICBASE_ENABLE; MSR_IA32_APICBASE_ENABLE 2008 arch/x86/kernel/apic/apic.c if (l & MSR_IA32_APICBASE_ENABLE) MSR_IA32_APICBASE_ENABLE 2030 arch/x86/kernel/apic/apic.c if (!(l & MSR_IA32_APICBASE_ENABLE)) { MSR_IA32_APICBASE_ENABLE 2033 arch/x86/kernel/apic/apic.c l |= MSR_IA32_APICBASE_ENABLE | addr; MSR_IA32_APICBASE_ENABLE 2686 arch/x86/kernel/apic/apic.c l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; MSR_IA32_APICBASE_ENABLE 84 arch/x86/kvm/cpuid.c if (vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE) MSR_IA32_APICBASE_ENABLE 2056 arch/x86/kvm/lapic.c if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) MSR_IA32_APICBASE_ENABLE 2124 arch/x86/kvm/lapic.c if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) MSR_IA32_APICBASE_ENABLE 2131 arch/x86/kvm/lapic.c if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) { MSR_IA32_APICBASE_ENABLE 2132 arch/x86/kvm/lapic.c if (value & MSR_IA32_APICBASE_ENABLE) { MSR_IA32_APICBASE_ENABLE 2144 arch/x86/kvm/lapic.c if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) MSR_IA32_APICBASE_ENABLE 2150 arch/x86/kvm/lapic.c if ((value & MSR_IA32_APICBASE_ENABLE) && MSR_IA32_APICBASE_ENABLE 2168 arch/x86/kvm/lapic.c MSR_IA32_APICBASE_ENABLE); MSR_IA32_APICBASE_ENABLE 2316 arch/x86/kvm/lapic.c vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; MSR_IA32_APICBASE_ENABLE 22 arch/x86/kvm/lapic.h LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE, MSR_IA32_APICBASE_ENABLE 23 arch/x86/kvm/lapic.h LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE, MSR_IA32_APICBASE_ENABLE 176 arch/x86/kvm/lapic.h return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; MSR_IA32_APICBASE_ENABLE 177 arch/x86/kvm/lapic.h return MSR_IA32_APICBASE_ENABLE; MSR_IA32_APICBASE_ENABLE 242 arch/x86/kvm/lapic.h return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); MSR_IA32_APICBASE_ENABLE 2150 arch/x86/kvm/svm.c MSR_IA32_APICBASE_ENABLE; MSR_IA32_APICBASE_ENABLE 4272 arch/x86/kvm/vmx/vmx.c MSR_IA32_APICBASE_ENABLE;