MSR_F15H_PERF_CTL  950 arch/x86/events/amd/core.c 	x86_pmu.eventsel	= MSR_F15H_PERF_CTL;
MSR_F15H_PERF_CTL  456 arch/x86/include/asm/msr-index.h #define MSR_F15H_PERF_CTL0		MSR_F15H_PERF_CTL
MSR_F15H_PERF_CTL  457 arch/x86/include/asm/msr-index.h #define MSR_F15H_PERF_CTL1		(MSR_F15H_PERF_CTL + 2)
MSR_F15H_PERF_CTL  458 arch/x86/include/asm/msr-index.h #define MSR_F15H_PERF_CTL2		(MSR_F15H_PERF_CTL + 4)
MSR_F15H_PERF_CTL  459 arch/x86/include/asm/msr-index.h #define MSR_F15H_PERF_CTL3		(MSR_F15H_PERF_CTL + 6)
MSR_F15H_PERF_CTL  460 arch/x86/include/asm/msr-index.h #define MSR_F15H_PERF_CTL4		(MSR_F15H_PERF_CTL + 8)
MSR_F15H_PERF_CTL  461 arch/x86/include/asm/msr-index.h #define MSR_F15H_PERF_CTL5		(MSR_F15H_PERF_CTL + 10)
MSR_F15H_PERF_CTL   80 arch/x86/kernel/cpu/perfctr-watchdog.c 		if (msr >= MSR_F15H_PERF_CTL)
MSR_F15H_PERF_CTL   81 arch/x86/kernel/cpu/perfctr-watchdog.c 			return (msr - MSR_F15H_PERF_CTL) >> 1;
MSR_F15H_PERF_CTL   55 arch/x86/kvm/pmu_amd.c 			return MSR_F15H_PERF_CTL;
MSR_F15H_PERF_CTL  316 arch/x86/oprofile/op_model_amd.c 			msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1);
MSR_F15H_PERF_CTL   78 arch/x86/xen/pmu.c 			amd_ctrls_base = MSR_F15H_PERF_CTL;
MSR_F15H_PERF_CTL  124 arch/x86/xen/pmu.c 		return MSR_F15H_PERF_CTL + (addr - MSR_K7_EVNTSEL0);
MSR_F15H_PERF_CTL  134 arch/x86/xen/pmu.c 	if ((msr >= MSR_F15H_PERF_CTL &&