MSR_ARCH_PERFMON_FIXED_CTR0 1072 arch/x86/events/core.c 		hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
MSR_ARCH_PERFMON_FIXED_CTR0 1404 arch/x86/events/core.c 		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
MSR_ARCH_PERFMON_FIXED_CTR0 2310 arch/x86/events/intel/core.c 		wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
MSR_ARCH_PERFMON_FIXED_CTR0 1219 arch/x86/kvm/x86.c 	MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
MSR_ARCH_PERFMON_FIXED_CTR0 1220 arch/x86/kvm/x86.c 	MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,