MSCIC_WRITE        32 arch/mips/kernel/irq-msc01.c 		MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
MSCIC_WRITE        34 arch/mips/kernel/irq-msc01.c 		MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
MSCIC_WRITE        43 arch/mips/kernel/irq-msc01.c 		MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
MSCIC_WRITE        45 arch/mips/kernel/irq-msc01.c 		MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
MSCIC_WRITE        55 arch/mips/kernel/irq-msc01.c 		MSCIC_WRITE(MSC01_IC_EOI, 0);
MSCIC_WRITE        67 arch/mips/kernel/irq-msc01.c 		MSCIC_WRITE(MSC01_IC_EOI, 0);
MSCIC_WRITE        71 arch/mips/kernel/irq-msc01.c 		MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
MSCIC_WRITE        72 arch/mips/kernel/irq-msc01.c 		MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
MSCIC_WRITE        94 arch/mips/kernel/irq-msc01.c 	MSCIC_WRITE(MSC01_IC_RAMW,
MSCIC_WRITE       122 arch/mips/kernel/irq-msc01.c 	MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
MSCIC_WRITE       136 arch/mips/kernel/irq-msc01.c 				MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
MSCIC_WRITE       138 arch/mips/kernel/irq-msc01.c 				MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
MSCIC_WRITE       146 arch/mips/kernel/irq-msc01.c 				MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
MSCIC_WRITE       148 arch/mips/kernel/irq-msc01.c 				MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
MSCIC_WRITE       154 arch/mips/kernel/irq-msc01.c 	MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT);	/* Enable interrupt generation */