MPLL_DQ_FUNC_CNTL 4041 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
MPLL_DQ_FUNC_CNTL 1062 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 								MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
MPLL_DQ_FUNC_CNTL 1064 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 								MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
MPLL_DQ_FUNC_CNTL 1090 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 								MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
MPLL_DQ_FUNC_CNTL 1092 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 								MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
MPLL_DQ_FUNC_CNTL  840 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 						MPLL_DQ_FUNC_CNTL, YCLK_SEL,
MPLL_DQ_FUNC_CNTL  843 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 						MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV,
MPLL_DQ_FUNC_CNTL 1889 drivers/gpu/drm/radeon/ci_dpm.c 	pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
MPLL_DQ_FUNC_CNTL 1193 drivers/gpu/drm/radeon/ni_dpm.c 	ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
MPLL_DQ_FUNC_CNTL  304 drivers/gpu/drm/radeon/rv740_dpm.c 		RREG32(MPLL_DQ_FUNC_CNTL);
MPLL_DQ_FUNC_CNTL 1535 drivers/gpu/drm/radeon/rv770_dpm.c 		RREG32(MPLL_DQ_FUNC_CNTL);
MPLL_DQ_FUNC_CNTL 3581 drivers/gpu/drm/radeon/si_dpm.c 	si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);