MOD_CONF_CTRL_1    49 arch/arm/mach-omap1/clock.c 	u32 div = omap_readl(MOD_CONF_CTRL_1);
MOD_CONF_CTRL_1   376 arch/arm/mach-omap1/clock.c 	l = omap_readl(MOD_CONF_CTRL_1);
MOD_CONF_CTRL_1   379 arch/arm/mach-omap1/clock.c 	omap_writel(l, MOD_CONF_CTRL_1);
MOD_CONF_CTRL_1   110 arch/arm/mach-omap1/clock_data.c 	.enable_reg	= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
MOD_CONF_CTRL_1   122 arch/arm/mach-omap1/devices.c 			omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24),
MOD_CONF_CTRL_1   123 arch/arm/mach-omap1/devices.c 					MOD_CONF_CTRL_1);
MOD_CONF_CTRL_1    51 arch/arm/mach-omap1/timer.c 	l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
MOD_CONF_CTRL_1    53 arch/arm/mach-omap1/timer.c 	omap_writel(l, MOD_CONF_CTRL_1);
MOD_CONF_CTRL_1   479 drivers/clocksource/timer-ti-dm.c 			if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
MOD_CONF_CTRL_1   595 drivers/video/fbdev/omap/sossi.c 	l = omap_readl(MOD_CONF_CTRL_1);
MOD_CONF_CTRL_1   597 drivers/video/fbdev/omap/sossi.c 	omap_writel(l, MOD_CONF_CTRL_1);
MOD_CONF_CTRL_1   599 drivers/video/fbdev/omap/sossi.c 	omap_writel(l, MOD_CONF_CTRL_1);