MMU_PAGE_2M        25 arch/powerpc/include/asm/book3s/64/hugetlb.h 	if (shift == mmu_psize_defs[MMU_PAGE_2M].shift)
MMU_PAGE_2M        26 arch/powerpc/include/asm/book3s/64/hugetlb.h 		return MMU_PAGE_2M;
MMU_PAGE_2M       127 arch/powerpc/include/asm/book3s/64/hugetlb.h 		if (mmu_psize != MMU_PAGE_2M && mmu_psize != MMU_PAGE_1G)
MMU_PAGE_2M       260 arch/powerpc/include/asm/book3s/64/radix.h 	if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
MMU_PAGE_2M      1128 arch/powerpc/kvm/book3s_64_mmu_radix.c 	add_rmmu_ap_encoding(info, MMU_PAGE_2M, &i);
MMU_PAGE_2M       166 arch/powerpc/mm/book3s64/hash_hugetlbpage.c 	else if (mmu_psize_defs[MMU_PAGE_2M].shift)
MMU_PAGE_2M       167 arch/powerpc/mm/book3s64/hash_hugetlbpage.c 		hpage_shift = mmu_psize_defs[MMU_PAGE_2M].shift;
MMU_PAGE_2M        50 arch/powerpc/mm/book3s64/pgtable.c 					pmd_pte(entry), address, MMU_PAGE_2M);
MMU_PAGE_2M       414 arch/powerpc/mm/book3s64/pgtable.c 		   atomic_long_read(&direct_pages_count[MMU_PAGE_2M]) << 11);
MMU_PAGE_2M       276 arch/powerpc/mm/book3s64/radix_pgtable.c 			   mmu_psize_defs[MMU_PAGE_2M].shift) {
MMU_PAGE_2M       278 arch/powerpc/mm/book3s64/radix_pgtable.c 			psize = MMU_PAGE_2M;
MMU_PAGE_2M       414 arch/powerpc/mm/book3s64/radix_pgtable.c 		idx = MMU_PAGE_2M;
MMU_PAGE_2M       554 arch/powerpc/mm/book3s64/radix_pgtable.c 	if (mmu_psize_defs[MMU_PAGE_2M].shift) {
MMU_PAGE_2M       558 arch/powerpc/mm/book3s64/radix_pgtable.c 		mmu_vmemmap_psize = MMU_PAGE_2M;
MMU_PAGE_2M       909 arch/powerpc/mm/book3s64/radix_tlb.c 						PMD_SIZE, MMU_PAGE_2M);
MMU_PAGE_2M       919 arch/powerpc/mm/book3s64/radix_tlb.c 						PMD_SIZE, MMU_PAGE_2M);
MMU_PAGE_2M       930 arch/powerpc/mm/book3s64/radix_tlb.c 					hstart, hend, pid, PMD_SIZE, MMU_PAGE_2M, false);
MMU_PAGE_2M       958 arch/powerpc/mm/book3s64/radix_tlb.c 	else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_2M].shift))
MMU_PAGE_2M       959 arch/powerpc/mm/book3s64/radix_tlb.c 		psize = MMU_PAGE_2M;
MMU_PAGE_2M      1188 arch/powerpc/mm/book3s64/radix_tlb.c 	radix__flush_tlb_range_psize(vma->vm_mm, start, end, MMU_PAGE_2M);
MMU_PAGE_2M        58 arch/powerpc/mm/nohash/tlb.c 	[MMU_PAGE_2M] = {
MMU_PAGE_2M       503 arch/powerpc/mm/nohash/tlb.c 				if (book3e_htw_mode && psize == MMU_PAGE_2M)
MMU_PAGE_2M       614 arch/powerpc/mm/nohash/tlb.c 		mmu_pte_psize = MMU_PAGE_2M;