MMIO_RING_DFH    1864 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL,
MMIO_RING_DFH    1872 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL);
MMIO_RING_DFH    1882 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
MMIO_RING_DFH    1886 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
MMIO_RING_DFH    1890 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
MMIO_RING_DFH    1899 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
MMIO_RING_DFH    1900 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
MMIO_RING_DFH    1901 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
MMIO_RING_DFH    1902 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);
MMIO_RING_DFH    1907 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
MMIO_RING_DFH    1911 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
MMIO_RING_DFH    1913 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
MMIO_RING_DFH    1915 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
MMIO_RING_DFH    1917 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
MMIO_RING_DFH    2662 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
MMIO_RING_DFH    2663 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
MMIO_RING_DFH    2741 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
MMIO_RING_DFH    2751 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
MMIO_RING_DFH    2760 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
MMIO_RING_DFH    2768 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
MMIO_RING_DFH    3098 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,