MMIO_DH 1874 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL, MMIO_DH 1892 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); MMIO_DH 1964 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); MMIO_DH 1965 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); MMIO_DH 1966 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); MMIO_DH 1967 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); MMIO_DH 2014 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); MMIO_DH 2017 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, MMIO_DH 2025 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); MMIO_DH 2028 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, MMIO_DH 2036 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); MMIO_DH 2039 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, MMIO_DH 2049 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); MMIO_DH 2054 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, MMIO_DH 2064 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); MMIO_DH 2069 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, MMIO_DH 2079 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); MMIO_DH 2084 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL, MMIO_DH 2209 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); MMIO_DH 2211 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); MMIO_DH 2212 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); MMIO_DH 2214 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); MMIO_DH 2215 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); MMIO_DH 2216 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); MMIO_DH 2217 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); MMIO_DH 2218 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); MMIO_DH 2219 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); MMIO_DH 2220 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); MMIO_DH 2221 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); MMIO_DH 2222 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); MMIO_DH 2272 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); MMIO_DH 2291 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); MMIO_DH 2292 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); MMIO_DH 2293 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); MMIO_DH 2294 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); MMIO_DH 2295 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); MMIO_DH 2296 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); MMIO_DH 2305 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); MMIO_DH 2317 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); MMIO_DH 2438 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); MMIO_DH 2440 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); MMIO_DH 2441 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); MMIO_DH 2447 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); MMIO_DH 2448 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); MMIO_DH 2449 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); MMIO_DH 2450 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); MMIO_DH 2451 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); MMIO_DH 2453 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); MMIO_DH 2454 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); MMIO_DH 2455 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); MMIO_DH 2456 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); MMIO_DH 2457 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); MMIO_DH 2459 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); MMIO_DH 2460 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); MMIO_DH 2461 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); MMIO_DH 2462 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); MMIO_DH 2463 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); MMIO_DH 2475 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); MMIO_DH 2476 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); MMIO_DH 2477 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); MMIO_DH 2478 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); MMIO_DH 2485 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); MMIO_DH 2491 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); MMIO_DH 2492 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); MMIO_DH 2494 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); MMIO_DH 2495 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); MMIO_DH 2524 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write); MMIO_DH 2525 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write); MMIO_DH 2526 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write); MMIO_DH 2527 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write); MMIO_DH 2528 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); MMIO_DH 2529 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); MMIO_DH 2533 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); MMIO_DH 2535 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); MMIO_DH 2546 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); MMIO_DH 2549 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); MMIO_DH 2565 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); MMIO_DH 2615 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); MMIO_DH 2650 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); MMIO_DH 2651 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); MMIO_DH 2652 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); MMIO_DH 2653 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); MMIO_DH 2654 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); MMIO_DH 2669 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); MMIO_DH 2670 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); MMIO_DH 2679 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); MMIO_DH 2680 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); MMIO_DH 2681 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); MMIO_DH 2684 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); MMIO_DH 2685 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); MMIO_DH 2686 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); MMIO_DH 2689 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); MMIO_DH 2690 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); MMIO_DH 2691 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); MMIO_DH 2694 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); MMIO_DH 2695 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); MMIO_DH 2696 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); MMIO_DH 2699 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, MMIO_DH 2701 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, MMIO_DH 2703 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, MMIO_DH 2707 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, MMIO_DH 2709 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, MMIO_DH 2711 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, MMIO_DH 2715 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, MMIO_DH 2717 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, MMIO_DH 2719 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, MMIO_DH 2723 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); MMIO_DH 2724 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); MMIO_DH 2725 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); MMIO_DH 2728 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); MMIO_DH 2729 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); MMIO_DH 2730 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); MMIO_DH 2733 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); MMIO_DH 2734 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); MMIO_DH 2735 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); MMIO_DH 2738 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, MMIO_DH 2779 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); MMIO_DH 2868 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); MMIO_DH 2869 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); MMIO_DH 2870 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); MMIO_DH 2871 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); MMIO_DH 2872 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); MMIO_DH 2873 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); MMIO_DH 2883 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write); MMIO_DH 2885 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DBUF_CTL, D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); MMIO_DH 2891 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(MMCD_MISC_CTRL, D_SKL_PLUS, NULL, NULL); MMIO_DH 2892 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL); MMIO_DH 2896 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); MMIO_DH 2897 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); MMIO_DH 2906 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL); MMIO_DH 2908 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2909 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2910 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2911 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2912 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2913 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2915 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2916 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2917 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2918 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2919 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2920 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2922 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2923 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2924 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2925 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2926 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2927 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); MMIO_DH 2929 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); MMIO_DH 2930 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); MMIO_DH 2931 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); MMIO_DH 2932 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); MMIO_DH 2934 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); MMIO_DH 2935 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); MMIO_DH 2936 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); MMIO_DH 2937 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); MMIO_DH 2939 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); MMIO_DH 2940 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); MMIO_DH 2941 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); MMIO_DH 2942 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); MMIO_DH 2944 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); MMIO_DH 2945 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); MMIO_DH 2946 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); MMIO_DH 2964 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); MMIO_DH 2965 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); MMIO_DH 2966 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); MMIO_DH 2968 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); MMIO_DH 2969 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); MMIO_DH 2970 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); MMIO_DH 2972 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); MMIO_DH 2973 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); MMIO_DH 2974 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); MMIO_DH 2976 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); MMIO_DH 2977 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); MMIO_DH 2978 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); MMIO_DH 2980 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); MMIO_DH 2981 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); MMIO_DH 2982 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); MMIO_DH 2983 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); MMIO_DH 2985 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); MMIO_DH 2986 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); MMIO_DH 2987 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); MMIO_DH 2988 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); MMIO_DH 2990 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); MMIO_DH 2991 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); MMIO_DH 2992 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); MMIO_DH 2993 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); MMIO_DH 2995 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); MMIO_DH 2996 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); MMIO_DH 2997 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); MMIO_DH 2998 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3000 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3001 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3002 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3003 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3005 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3006 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3007 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3008 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3010 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3011 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3012 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3013 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3015 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3016 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3017 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3018 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3020 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3021 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3022 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3023 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); MMIO_DH 3061 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write); MMIO_DH 3069 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); MMIO_DH 3142 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write); MMIO_DH 3144 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, MMIO_DH 3146 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, MMIO_DH 3151 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, MMIO_DH 3153 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, MMIO_DH 3155 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL, MMIO_DH 3184 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, MMIO_DH 3188 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT, MMIO_DH 3212 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, MMIO_DH 3216 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT, MMIO_DH 3240 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, MMIO_DH 3244 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT, MMIO_DH 3263 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);