MMHUB_BASE         37 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c 		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
MMHUB_BASE         37 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c 		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
MMHUB_BASE         37 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
MMHUB_BASE         37 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
MMHUB_BASE         37 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
MMHUB_BASE         37 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
MMHUB_BASE        153 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 		.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) +  \
MMHUB_BASE        201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) +  \
MMHUB_BASE        462 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
MMHUB_BASE        325 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
MMHUB_BASE         87 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE MMHUB_BASE            ={ { { { 0x00012440, 0x0001A000, 0x00408800, 0, 0, 0 } },
MMHUB_BASE         79 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE MMHUB_BASE            ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } },
MMHUB_BASE        109 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
MMHUB_BASE        109 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
MMHUB_BASE        144 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
MMHUB_BASE        148 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE MMHUB_BASE			= { { { { 0x0001A000, 0, 0, 0, 0 } },
MMHUB_BASE         81 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE MMHUB_BASE            ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } },