MLX5_CAP_ETH 905 drivers/infiniband/hw/mlx5/main.c if (MLX5_CAP_ETH(mdev, csum_cap)) { MLX5_CAP_ETH 911 drivers/infiniband/hw/mlx5/main.c if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) MLX5_CAP_ETH 916 drivers/infiniband/hw/mlx5/main.c max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); MLX5_CAP_ETH 966 drivers/infiniband/hw/mlx5/main.c MLX5_CAP_ETH(dev->mdev, scatter_fcs) && MLX5_CAP_ETH 1108 drivers/infiniband/hw/mlx5/main.c if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) MLX5_CAP_ETH 1112 drivers/infiniband/hw/mlx5/main.c if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) MLX5_CAP_ETH 1138 drivers/infiniband/hw/mlx5/main.c if (MLX5_CAP_ETH(mdev, swp)) { MLX5_CAP_ETH 1142 drivers/infiniband/hw/mlx5/main.c if (MLX5_CAP_ETH(mdev, swp_csum)) MLX5_CAP_ETH 1146 drivers/infiniband/hw/mlx5/main.c if (MLX5_CAP_ETH(mdev, swp_lso)) MLX5_CAP_ETH 1175 drivers/infiniband/hw/mlx5/main.c if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) MLX5_CAP_ETH 1178 drivers/infiniband/hw/mlx5/main.c if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) MLX5_CAP_ETH 1181 drivers/infiniband/hw/mlx5/main.c if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) MLX5_CAP_ETH 1184 drivers/infiniband/hw/mlx5/main.c if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) MLX5_CAP_ETH 1187 drivers/infiniband/hw/mlx5/main.c if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) MLX5_CAP_ETH 1253 drivers/infiniband/hw/mlx5/qp.c if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) MLX5_CAP_ETH 1261 drivers/infiniband/hw/mlx5/qp.c MLX5_CAP_ETH(dev->mdev, swp)) MLX5_CAP_ETH 1382 drivers/infiniband/hw/mlx5/qp.c return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || MLX5_CAP_ETH 1383 drivers/infiniband/hw/mlx5/qp.c MLX5_CAP_ETH(dev, tunnel_stateless_gre) || MLX5_CAP_ETH 1384 drivers/infiniband/hw/mlx5/qp.c MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); MLX5_CAP_ETH 2020 drivers/infiniband/hw/mlx5/qp.c !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { MLX5_CAP_ETH 2032 drivers/infiniband/hw/mlx5/qp.c MLX5_CAP_ETH(dev->mdev, vlan_cap)) || MLX5_CAP_ETH 5975 drivers/infiniband/hw/mlx5/qp.c if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { MLX5_CAP_ETH 5984 drivers/infiniband/hw/mlx5/qp.c if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { MLX5_CAP_ETH 6333 drivers/infiniband/hw/mlx5/qp.c MLX5_CAP_ETH(dev->mdev, vlan_cap))) { MLX5_CAP_ETH 1075 drivers/net/ethernet/mellanox/mlx5/core/en.h return MLX5_CAP_ETH(mdev, swp) && MLX5_CAP_ETH 1076 drivers/net/ethernet/mellanox/mlx5/core/en.h MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso); MLX5_CAP_ETH 522 drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c !MLX5_CAP_ETH(mdev, swp)) { MLX5_CAP_ETH 532 drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c if (!MLX5_CAP_ETH(mdev, swp_csum)) { MLX5_CAP_ETH 541 drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c !MLX5_CAP_ETH(mdev, swp_lso)) { MLX5_CAP_ETH 1875 drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) MLX5_CAP_ETH 773 drivers/net/ethernet/mellanox/mlx5/core/en_fs.c return MLX5_CAP_ETH(mdev, tunnel_stateless_gre); MLX5_CAP_ETH 776 drivers/net/ethernet/mellanox/mlx5/core/en_fs.c return MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip); MLX5_CAP_ETH 72 drivers/net/ethernet/mellanox/mlx5/core/en_main.c MLX5_CAP_ETH(mdev, reg_umr_sq); MLX5_CAP_ETH 900 drivers/net/ethernet/mellanox/mlx5/core/en_main.c if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full)) MLX5_CAP_ETH 1155 drivers/net/ethernet/mellanox/mlx5/core/en_main.c if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert)) MLX5_CAP_ETH 1228 drivers/net/ethernet/mellanox/mlx5/core/en_main.c if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) MLX5_CAP_ETH 2301 drivers/net/ethernet/mellanox/mlx5/core/en_main.c MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq)); MLX5_CAP_ETH 4641 drivers/net/ethernet/mellanox/mlx5/core/en_main.c !MLX5_CAP_ETH(mdev, csum_cap) || MLX5_CAP_ETH 4642 drivers/net/ethernet/mellanox/mlx5/core/en_main.c !MLX5_CAP_ETH(mdev, max_lso_cap) || MLX5_CAP_ETH 4643 drivers/net/ethernet/mellanox/mlx5/core/en_main.c !MLX5_CAP_ETH(mdev, vlan_cap) || MLX5_CAP_ETH 4644 drivers/net/ethernet/mellanox/mlx5/core/en_main.c !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) || MLX5_CAP_ETH 4652 drivers/net/ethernet/mellanox/mlx5/core/en_main.c if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable)) MLX5_CAP_ETH 4754 drivers/net/ethernet/mellanox/mlx5/core/en_main.c if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout) MLX5_CAP_ETH 4757 drivers/net/ethernet/mellanox/mlx5/core/en_main.c return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]); MLX5_CAP_ETH 4814 drivers/net/ethernet/mellanox/mlx5/core/en_main.c MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)); MLX5_CAP_ETH 4907 drivers/net/ethernet/mellanox/mlx5/core/en_main.c if (!!MLX5_CAP_ETH(mdev, lro_cap) && MLX5_CAP_ETH 4961 drivers/net/ethernet/mellanox/mlx5/core/en_main.c if (MLX5_CAP_ETH(mdev, scatter_fcs)) MLX5_CAP_ETH 2367 drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) { MLX5_CAP_ETH 2436 drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) { MLX5_CAP_ETH 58 drivers/net/ethernet/mellanox/mlx5/core/lib/vxlan.c return MLX5_CAP_ETH(mdev, max_vxlan_udp_ports) ?: 4; MLX5_CAP_ETH 197 drivers/net/ethernet/mellanox/mlx5/core/lib/vxlan.c if (!MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || !mlx5_core_is_pf(mdev)) MLX5_CAP_ETH 124 drivers/net/ethernet/mellanox/mlx5/core/vport.c switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {