MI_LOAD_REGISTER_IMM 1000 drivers/gpu/drm/i915/gem/i915_gem_context.c *cs++ = MI_LOAD_REGISTER_IMM(2); MI_LOAD_REGISTER_IMM 1016 drivers/gpu/drm/i915/gem/i915_gem_context.c *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES); MI_LOAD_REGISTER_IMM 1952 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c *cs++ = MI_LOAD_REGISTER_IMM(4); MI_LOAD_REGISTER_IMM 1933 drivers/gpu/drm/i915/gt/intel_lrc.c *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED; MI_LOAD_REGISTER_IMM 2015 drivers/gpu/drm/i915/gt/intel_lrc.c *batch++ = MI_LOAD_REGISTER_IMM(1); MI_LOAD_REGISTER_IMM 2096 drivers/gpu/drm/i915/gt/intel_lrc.c *batch++ = MI_LOAD_REGISTER_IMM(count); MI_LOAD_REGISTER_IMM 3207 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) | MI_LOAD_REGISTER_IMM 3255 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; MI_LOAD_REGISTER_IMM 3282 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); MI_LOAD_REGISTER_IMM 451 drivers/gpu/drm/i915/gt/intel_mocs.c *cs++ = MI_LOAD_REGISTER_IMM(table->n_entries); MI_LOAD_REGISTER_IMM 509 drivers/gpu/drm/i915/gt/intel_mocs.c *cs++ = MI_LOAD_REGISTER_IMM(table->n_entries / 2); MI_LOAD_REGISTER_IMM 1539 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = MI_LOAD_REGISTER_IMM(1); MI_LOAD_REGISTER_IMM 1543 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = MI_LOAD_REGISTER_IMM(1); MI_LOAD_REGISTER_IMM 1613 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = MI_LOAD_REGISTER_IMM(num_engines); MI_LOAD_REGISTER_IMM 1667 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = MI_LOAD_REGISTER_IMM(num_engines); MI_LOAD_REGISTER_IMM 1712 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); MI_LOAD_REGISTER_IMM 636 drivers/gpu/drm/i915/gt/intel_workarounds.c *cs++ = MI_LOAD_REGISTER_IMM(wal->count); MI_LOAD_REGISTER_IMM 518 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = MI_LOAD_REGISTER_IMM(1); MI_LOAD_REGISTER_IMM 531 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = MI_LOAD_REGISTER_IMM(1); MI_LOAD_REGISTER_IMM 826 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = MI_LOAD_REGISTER_IMM(whitelist_writable_count(engine)); MI_LOAD_REGISTER_IMM 213 drivers/gpu/drm/i915/gvt/mmio_context.c *cs++ = MI_LOAD_REGISTER_IMM(count); MI_LOAD_REGISTER_IMM 248 drivers/gpu/drm/i915/gvt/mmio_context.c *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE); MI_LOAD_REGISTER_IMM 275 drivers/gpu/drm/i915/gvt/mmio_context.c *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2); MI_LOAD_REGISTER_IMM 219 drivers/gpu/drm/i915/i915_cmd_parser.c CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, MI_LOAD_REGISTER_IMM 476 drivers/gpu/drm/i915/i915_cmd_parser.c CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, MI_LOAD_REGISTER_IMM 1256 drivers/gpu/drm/i915/i915_cmd_parser.c if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) && MI_LOAD_REGISTER_IMM 1754 drivers/gpu/drm/i915/i915_perf.c *cs++ = MI_LOAD_REGISTER_IMM(count);