MI_INSTR           37 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_NOOP			MI_INSTR(0, 0)
MI_INSTR           38 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
MI_INSTR           39 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
MI_INSTR           44 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_FLUSH		MI_INSTR(0x04, 0)
MI_INSTR           51 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
MI_INSTR           52 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)
MI_INSTR           55 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
MI_INSTR           56 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
MI_INSTR           58 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_SET_APPID		MI_INSTR(0x0e, 0)
MI_INSTR           59 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)
MI_INSTR           63 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
MI_INSTR           64 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
MI_INSTR           65 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)
MI_INSTR           84 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6, gen7 */
MI_INSTR          103 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
MI_INSTR          112 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_SEMAPHORE_SIGNAL	MI_INSTR(0x1b, 0) /* GEN8+ */
MI_INSTR          114 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */
MI_INSTR          122 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
MI_INSTR          123 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_STORE_DWORD_IMM_GEN4	MI_INSTR(0x20, 2)
MI_INSTR          126 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
MI_INSTR          134 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*(x)-1)
MI_INSTR          136 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_STORE_REGISTER_MEM        MI_INSTR(0x24, 1)
MI_INSTR          137 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_STORE_REGISTER_MEM_GEN8   MI_INSTR(0x24, 2)
MI_INSTR          139 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
MI_INSTR          148 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_LOAD_REGISTER_MEM	   MI_INSTR(0x29, 1)
MI_INSTR          149 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_LOAD_REGISTER_MEM_GEN8  MI_INSTR(0x29, 2)
MI_INSTR          150 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
MI_INSTR          156 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
MI_INSTR          158 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)
MI_INSTR          241 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_SET_PREDICATE        MI_INSTR(0x01, 0)
MI_INSTR          242 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_ARB_CHECK            MI_INSTR(0x05, 0)
MI_INSTR          243 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_RS_CONTROL           MI_INSTR(0x06, 0)
MI_INSTR          244 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_URB_ATOMIC_ALLOC     MI_INSTR(0x09, 0)
MI_INSTR          245 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_PREDICATE            MI_INSTR(0x0C, 0)
MI_INSTR          246 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_RS_CONTEXT           MI_INSTR(0x0F, 0)
MI_INSTR          247 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_TOPOLOGY_FILTER      MI_INSTR(0x0D, 0)
MI_INSTR          248 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
MI_INSTR          249 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_URB_CLEAR            MI_INSTR(0x19, 0)
MI_INSTR          250 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_UPDATE_GTT           MI_INSTR(0x23, 0)
MI_INSTR          251 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_CLFLUSH              MI_INSTR(0x27, 0)
MI_INSTR          252 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_REPORT_PERF_COUNT    MI_INSTR(0x28, 0)
MI_INSTR          254 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_LOAD_REGISTER_REG    MI_INSTR(0x2A, 0)
MI_INSTR          255 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_RS_STORE_DATA_IMM    MI_INSTR(0x2B, 0)
MI_INSTR          256 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_LOAD_URB_MEM         MI_INSTR(0x2C, 0)
MI_INSTR          257 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_STORE_URB_MEM        MI_INSTR(0x2D, 0)
MI_INSTR          258 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)