MIPS_CPU_IRQ_BASE 917 arch/mips/alchemy/common/irq.c irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, au1000_ic0r0_dispatch); MIPS_CPU_IRQ_BASE 918 arch/mips/alchemy/common/irq.c irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, au1000_ic0r1_dispatch); MIPS_CPU_IRQ_BASE 919 arch/mips/alchemy/common/irq.c irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, au1000_ic1r0_dispatch); MIPS_CPU_IRQ_BASE 920 arch/mips/alchemy/common/irq.c irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, au1000_ic1r1_dispatch); MIPS_CPU_IRQ_BASE 957 arch/mips/alchemy/common/irq.c irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, alchemy_gpic_dispatch); MIPS_CPU_IRQ_BASE 958 arch/mips/alchemy/common/irq.c irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, alchemy_gpic_dispatch); MIPS_CPU_IRQ_BASE 959 arch/mips/alchemy/common/irq.c irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, alchemy_gpic_dispatch); MIPS_CPU_IRQ_BASE 960 arch/mips/alchemy/common/irq.c irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, alchemy_gpic_dispatch); MIPS_CPU_IRQ_BASE 995 arch/mips/alchemy/common/irq.c do_IRQ(MIPS_CPU_IRQ_BASE + __ffs(r & 0xff)); MIPS_CPU_IRQ_BASE 20 arch/mips/ath25/ar2315_regs.h #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */ MIPS_CPU_IRQ_BASE 21 arch/mips/ath25/ar2315_regs.h #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */ MIPS_CPU_IRQ_BASE 22 arch/mips/ath25/ar2315_regs.h #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */ MIPS_CPU_IRQ_BASE 23 arch/mips/ath25/ar2315_regs.h #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */ MIPS_CPU_IRQ_BASE 24 arch/mips/ath25/ar2315_regs.h #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */ MIPS_CPU_IRQ_BASE 17 arch/mips/ath25/ar5312_regs.h #define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */ MIPS_CPU_IRQ_BASE 18 arch/mips/ath25/ar5312_regs.h #define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */ MIPS_CPU_IRQ_BASE 19 arch/mips/ath25/ar5312_regs.h #define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */ MIPS_CPU_IRQ_BASE 20 arch/mips/ath25/ar5312_regs.h #define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */ MIPS_CPU_IRQ_BASE 21 arch/mips/ath25/ar5312_regs.h #define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */ MIPS_CPU_IRQ_BASE 9 arch/mips/ath25/devices.h #define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */ MIPS_CPU_IRQ_BASE 548 arch/mips/bcm63xx/irq.c setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action); MIPS_CPU_IRQ_BASE 551 arch/mips/bcm63xx/irq.c setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action); MIPS_CPU_IRQ_BASE 554 arch/mips/bcm63xx/irq.c setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action); MIPS_CPU_IRQ_BASE 2957 arch/mips/cavium-octeon/octeon-irq.c do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE); MIPS_CPU_IRQ_BASE 37 arch/mips/cobalt/irq.c do_IRQ(MIPS_CPU_IRQ_BASE + 3); MIPS_CPU_IRQ_BASE 39 arch/mips/cobalt/irq.c do_IRQ(MIPS_CPU_IRQ_BASE + 4); MIPS_CPU_IRQ_BASE 41 arch/mips/cobalt/irq.c do_IRQ(MIPS_CPU_IRQ_BASE + 5); MIPS_CPU_IRQ_BASE 43 arch/mips/cobalt/irq.c do_IRQ(MIPS_CPU_IRQ_BASE + 7); MIPS_CPU_IRQ_BASE 277 arch/mips/emma/markeins/irq.c setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade); MIPS_CPU_IRQ_BASE 285 arch/mips/emma/markeins/irq.c do_IRQ(MIPS_CPU_IRQ_BASE + 7); MIPS_CPU_IRQ_BASE 289 arch/mips/emma/markeins/irq.c do_IRQ(MIPS_CPU_IRQ_BASE + 1); MIPS_CPU_IRQ_BASE 291 arch/mips/emma/markeins/irq.c do_IRQ(MIPS_CPU_IRQ_BASE + 0); MIPS_CPU_IRQ_BASE 26 arch/mips/generic/irq.c mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq; MIPS_CPU_IRQ_BASE 42 arch/mips/generic/irq.c mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; MIPS_CPU_IRQ_BASE 58 arch/mips/generic/irq.c mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; MIPS_CPU_IRQ_BASE 91 arch/mips/include/asm/dec/interrupts.h #define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */ MIPS_CPU_IRQ_BASE 91 arch/mips/include/asm/emma/emma2rh.h #define EMMA2RH_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) MIPS_CPU_IRQ_BASE 25 arch/mips/include/asm/ip32/ip32_ints.h CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE + 8, MIPS_CPU_IRQ_BASE 206 arch/mips/include/asm/jazz.h #define JAZZ_TIMER_IRQ (MIPS_CPU_IRQ_BASE+6) MIPS_CPU_IRQ_BASE 12 arch/mips/include/asm/mach-ath79/irq.h #define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x)) MIPS_CPU_IRQ_BASE 39 arch/mips/include/asm/mach-au1x00/au1000.h #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) MIPS_CPU_IRQ_BASE 46 arch/mips/include/asm/mach-au1x00/au1000.h #define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8) MIPS_CPU_IRQ_BASE 42 arch/mips/include/asm/mach-cobalt/irq.h #define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2) MIPS_CPU_IRQ_BASE 43 arch/mips/include/asm/mach-cobalt/irq.h #define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3) MIPS_CPU_IRQ_BASE 44 arch/mips/include/asm/mach-cobalt/irq.h #define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3) MIPS_CPU_IRQ_BASE 45 arch/mips/include/asm/mach-cobalt/irq.h #define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4) MIPS_CPU_IRQ_BASE 46 arch/mips/include/asm/mach-cobalt/irq.h #define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4) MIPS_CPU_IRQ_BASE 47 arch/mips/include/asm/mach-cobalt/irq.h #define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5) MIPS_CPU_IRQ_BASE 48 arch/mips/include/asm/mach-cobalt/irq.h #define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5) MIPS_CPU_IRQ_BASE 49 arch/mips/include/asm/mach-cobalt/irq.h #define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6) MIPS_CPU_IRQ_BASE 16 arch/mips/include/asm/mach-db1x00/irq.h #ifndef MIPS_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE 23 arch/mips/include/asm/mach-generic/irq.h #ifndef MIPS_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE 33 arch/mips/include/asm/mach-generic/irq.h #define RM7K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+8) MIPS_CPU_IRQ_BASE 41 arch/mips/include/asm/mach-generic/irq.h #define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) MIPS_CPU_IRQ_BASE 17 arch/mips/include/asm/mach-ip27/irq.h #define IP27_HUB_PEND0_IRQ (MIPS_CPU_IRQ_BASE + 2) MIPS_CPU_IRQ_BASE 18 arch/mips/include/asm/mach-ip27/irq.h #define IP27_HUB_PEND1_IRQ (MIPS_CPU_IRQ_BASE + 3) MIPS_CPU_IRQ_BASE 19 arch/mips/include/asm/mach-ip27/irq.h #define IP27_RT_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 4) MIPS_CPU_IRQ_BASE 21 arch/mips/include/asm/mach-ip27/irq.h #define IP27_HUB_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) MIPS_CPU_IRQ_BASE 5 arch/mips/include/asm/mach-lasat/irq.h #define LASAT_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2) MIPS_CPU_IRQ_BASE 15 arch/mips/include/asm/mach-loongson32/irq.h #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) MIPS_CPU_IRQ_BASE 26 arch/mips/include/asm/mach-loongson32/irq.h #define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE) MIPS_CPU_IRQ_BASE 12 arch/mips/include/asm/mach-loongson64/irq.h #define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */ MIPS_CPU_IRQ_BASE 13 arch/mips/include/asm/mach-loongson64/irq.h #define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */ MIPS_CPU_IRQ_BASE 14 arch/mips/include/asm/mach-loongson64/irq.h #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */ MIPS_CPU_IRQ_BASE 68 arch/mips/include/asm/mach-loongson64/loongson.h #define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */ MIPS_CPU_IRQ_BASE 14 arch/mips/include/asm/mach-paravirt/irq.h #define MIPS_IRQ_PCIA (MIPS_CPU_IRQ_BASE + 8) MIPS_CPU_IRQ_BASE 16 arch/mips/include/asm/mach-paravirt/irq.h #define MIPS_IRQ_MBOX0 (MIPS_CPU_IRQ_BASE + 32) MIPS_CPU_IRQ_BASE 17 arch/mips/include/asm/mach-paravirt/irq.h #define MIPS_IRQ_MBOX1 (MIPS_CPU_IRQ_BASE + 33) MIPS_CPU_IRQ_BASE 29 arch/mips/include/asm/mach-pnx833x/irq-mapping.h #define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) MIPS_CPU_IRQ_BASE 36 arch/mips/include/asm/mach-pnx833x/irq.h #define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ) MIPS_CPU_IRQ_BASE 34 arch/mips/include/asm/mach-ralink/mt7621.h #define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) MIPS_CPU_IRQ_BASE 28 arch/mips/include/asm/sgi/ip22.h #define SGINT_CPU MIPS_CPU_IRQ_BASE /* MIPS CPU define 8 interrupt sources */ MIPS_CPU_IRQ_BASE 144 arch/mips/include/asm/sni.h #define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE 152 arch/mips/include/asm/sni.h #define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5) MIPS_CPU_IRQ_BASE 177 arch/mips/include/asm/sni.h #define PCIMT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE+6) MIPS_CPU_IRQ_BASE 15 arch/mips/include/asm/txx9irq.h #define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) MIPS_CPU_IRQ_BASE 20 arch/mips/include/asm/vr41xx/irq.h #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) MIPS_CPU_IRQ_BASE 250 arch/mips/kernel/cevt-r4k.c return MIPS_CPU_IRQ_BASE + cp0_compare_irq; MIPS_CPU_IRQ_BASE 1705 arch/mips/kernel/perf_event_mipsxx.c irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; MIPS_CPU_IRQ_BASE 26 arch/mips/kernel/rtlx-mt.c do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); MIPS_CPU_IRQ_BASE 59 arch/mips/kernel/rtlx-mt.c static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ; MIPS_CPU_IRQ_BASE 68 arch/mips/kernel/smp-bmips.c #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0) MIPS_CPU_IRQ_BASE 69 arch/mips/kernel/smp-bmips.c #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1) MIPS_CPU_IRQ_BASE 33 arch/mips/loongson64/common/serial.c .irq = MIPS_CPU_IRQ_BASE + (int), \ MIPS_CPU_IRQ_BASE 87 arch/mips/loongson64/common/serial.c MIPS_CPU_IRQ_BASE + loongson_sysconf.uarts[i].int_offset; MIPS_CPU_IRQ_BASE 27 arch/mips/loongson64/fuloong-2e/irq.c do_IRQ(MIPS_CPU_IRQ_BASE + 7); MIPS_CPU_IRQ_BASE 62 arch/mips/loongson64/fuloong-2e/irq.c setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); MIPS_CPU_IRQ_BASE 64 arch/mips/loongson64/fuloong-2e/irq.c setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); MIPS_CPU_IRQ_BASE 18 arch/mips/loongson64/lemote-2f/irq.c #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */ MIPS_CPU_IRQ_BASE 19 arch/mips/loongson64/lemote-2f/irq.c #define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */ MIPS_CPU_IRQ_BASE 20 arch/mips/loongson64/lemote-2f/irq.c #define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */ MIPS_CPU_IRQ_BASE 21 arch/mips/loongson64/lemote-2f/irq.c #define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */ MIPS_CPU_IRQ_BASE 218 arch/mips/mti-malta/malta-int.c corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; MIPS_CPU_IRQ_BASE 223 arch/mips/mti-malta/malta-int.c corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; MIPS_CPU_IRQ_BASE 48 arch/mips/mti-malta/malta-platform.c .irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2, MIPS_CPU_IRQ_BASE 148 arch/mips/mti-malta/malta-time.c return MIPS_CPU_IRQ_BASE + cp0_fdc_irq; MIPS_CPU_IRQ_BASE 161 arch/mips/mti-malta/malta-time.c mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; MIPS_CPU_IRQ_BASE 178 arch/mips/mti-malta/malta-time.c mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; MIPS_CPU_IRQ_BASE 443 arch/mips/oprofile/op_model_mipsxx.c perfcount_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; MIPS_CPU_IRQ_BASE 142 arch/mips/paravirt/paravirt-irq.c irq = MIPS_CPU_IRQ_BASE + i; MIPS_CPU_IRQ_BASE 367 arch/mips/paravirt/paravirt-irq.c do_IRQ(MIPS_CPU_IRQ_BASE + ip); MIPS_CPU_IRQ_BASE 276 arch/mips/pnx833x/common/interrupts.c mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; MIPS_CPU_IRQ_BASE 23 arch/mips/ralink/irq.c #define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2) MIPS_CPU_IRQ_BASE 24 arch/mips/ralink/irq.c #define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4) MIPS_CPU_IRQ_BASE 25 arch/mips/ralink/irq.c #define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5) MIPS_CPU_IRQ_BASE 26 arch/mips/ralink/irq.c #define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6) MIPS_CPU_IRQ_BASE 27 arch/mips/ralink/irq.c #define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7) MIPS_CPU_IRQ_BASE 415 arch/mips/sgi-ip32/ip32-irq.c do_IRQ(MIPS_CPU_IRQ_BASE + 7); MIPS_CPU_IRQ_BASE 311 arch/mips/sibyte/sb1250/irq.c do_IRQ(MIPS_CPU_IRQ_BASE + 7); MIPS_CPU_IRQ_BASE 281 arch/mips/sni/pcimt.c do_IRQ(MIPS_CPU_IRQ_BASE + 7); MIPS_CPU_IRQ_BASE 283 arch/mips/sni/pcimt.c do_IRQ(MIPS_CPU_IRQ_BASE + 6); MIPS_CPU_IRQ_BASE 214 arch/mips/sni/pcit.c do_IRQ(MIPS_CPU_IRQ_BASE + 4); MIPS_CPU_IRQ_BASE 216 arch/mips/sni/pcit.c do_IRQ(MIPS_CPU_IRQ_BASE + 5); MIPS_CPU_IRQ_BASE 218 arch/mips/sni/pcit.c do_IRQ(MIPS_CPU_IRQ_BASE + 7); MIPS_CPU_IRQ_BASE 228 arch/mips/sni/pcit.c do_IRQ(MIPS_CPU_IRQ_BASE + 3); MIPS_CPU_IRQ_BASE 230 arch/mips/sni/pcit.c do_IRQ(MIPS_CPU_IRQ_BASE + 4); MIPS_CPU_IRQ_BASE 232 arch/mips/sni/pcit.c do_IRQ(MIPS_CPU_IRQ_BASE + 5); MIPS_CPU_IRQ_BASE 234 arch/mips/sni/pcit.c do_IRQ(MIPS_CPU_IRQ_BASE + 7); MIPS_CPU_IRQ_BASE 260 arch/mips/sni/pcit.c setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq); MIPS_CPU_IRQ_BASE 458 arch/mips/sni/rm200.c do_IRQ(MIPS_CPU_IRQ_BASE + 7); MIPS_CPU_IRQ_BASE 38 arch/mips/txx9/generic/irq_tx4927.c irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, MIPS_CPU_IRQ_BASE 26 arch/mips/txx9/generic/irq_tx4938.c irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, MIPS_CPU_IRQ_BASE 196 arch/mips/txx9/generic/irq_tx4939.c irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT, MIPS_CPU_IRQ_BASE 177 arch/mips/txx9/rbtx4927/irq.c irq = MIPS_CPU_IRQ_BASE + 7; MIPS_CPU_IRQ_BASE 183 arch/mips/txx9/rbtx4927/irq.c irq = MIPS_CPU_IRQ_BASE + 0; MIPS_CPU_IRQ_BASE 185 arch/mips/txx9/rbtx4927/irq.c irq = MIPS_CPU_IRQ_BASE + 1; MIPS_CPU_IRQ_BASE 115 arch/mips/txx9/rbtx4938/irq.c irq = MIPS_CPU_IRQ_BASE + 7; MIPS_CPU_IRQ_BASE 121 arch/mips/txx9/rbtx4938/irq.c irq = MIPS_CPU_IRQ_BASE + 0; MIPS_CPU_IRQ_BASE 123 arch/mips/txx9/rbtx4938/irq.c irq = MIPS_CPU_IRQ_BASE + 1; MIPS_CPU_IRQ_BASE 58 arch/mips/txx9/rbtx4939/irq.c return MIPS_CPU_IRQ_BASE + 7; MIPS_CPU_IRQ_BASE 68 arch/mips/txx9/rbtx4939/irq.c irq = MIPS_CPU_IRQ_BASE + 0; MIPS_CPU_IRQ_BASE 70 arch/mips/txx9/rbtx4939/irq.c irq = MIPS_CPU_IRQ_BASE + 1; MIPS_CPU_IRQ_BASE 51 drivers/irqchip/irq-ath79-cpu.c do_IRQ(MIPS_CPU_IRQ_BASE + irq); MIPS_CPU_IRQ_BASE 254 drivers/irqchip/irq-mips-cpu.c irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, MIPS_CPU_IRQ_BASE 118 drivers/irqchip/irq-mips-gic.c return MIPS_CPU_IRQ_BASE + cp0_compare_irq; MIPS_CPU_IRQ_BASE 129 drivers/irqchip/irq-mips-gic.c return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; MIPS_CPU_IRQ_BASE 141 drivers/irqchip/irq-mips-gic.c return MIPS_CPU_IRQ_BASE + cp0_fdc_irq; MIPS_CPU_IRQ_BASE 734 drivers/irqchip/irq-mips-gic.c irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, MIPS_CPU_IRQ_BASE 750 drivers/irqchip/irq-mips-gic.c irq_set_chained_handler(MIPS_CPU_IRQ_BASE +