MIN_POST_DIVR_FREQ   81 drivers/clk/analogbits/wrpll-cln28hpc.c 	if (post_divr_freq < MIN_POST_DIVR_FREQ ||
MIN_POST_DIVR_FREQ  188 drivers/clk/analogbits/wrpll-cln28hpc.c 	if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ)
MIN_POST_DIVR_FREQ  192 drivers/clk/analogbits/wrpll-cln28hpc.c 	max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ);