MIDR_CPU_MODEL     96 arch/arm64/include/asm/cputype.h #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
MIDR_CPU_MODEL     97 arch/arm64/include/asm/cputype.h #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
MIDR_CPU_MODEL     98 arch/arm64/include/asm/cputype.h #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
MIDR_CPU_MODEL     99 arch/arm64/include/asm/cputype.h #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
MIDR_CPU_MODEL    100 arch/arm64/include/asm/cputype.h #define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
MIDR_CPU_MODEL    101 arch/arm64/include/asm/cputype.h #define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
MIDR_CPU_MODEL    102 arch/arm64/include/asm/cputype.h #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
MIDR_CPU_MODEL    103 arch/arm64/include/asm/cputype.h #define MIDR_CORTEX_A76	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
MIDR_CPU_MODEL    104 arch/arm64/include/asm/cputype.h #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
MIDR_CPU_MODEL    105 arch/arm64/include/asm/cputype.h #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
MIDR_CPU_MODEL    106 arch/arm64/include/asm/cputype.h #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
MIDR_CPU_MODEL    107 arch/arm64/include/asm/cputype.h #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
MIDR_CPU_MODEL    108 arch/arm64/include/asm/cputype.h #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
MIDR_CPU_MODEL    109 arch/arm64/include/asm/cputype.h #define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
MIDR_CPU_MODEL    110 arch/arm64/include/asm/cputype.h #define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
MIDR_CPU_MODEL    111 arch/arm64/include/asm/cputype.h #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
MIDR_CPU_MODEL    112 arch/arm64/include/asm/cputype.h #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
MIDR_CPU_MODEL    113 arch/arm64/include/asm/cputype.h #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
MIDR_CPU_MODEL    114 arch/arm64/include/asm/cputype.h #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
MIDR_CPU_MODEL    115 arch/arm64/include/asm/cputype.h #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
MIDR_CPU_MODEL    116 arch/arm64/include/asm/cputype.h #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
MIDR_CPU_MODEL    117 arch/arm64/include/asm/cputype.h #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)