MHL_TX_INT_CTRL_REG  312 drivers/gpu/drm/bridge/sii9234.c 	mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, enable ? ~0 : 0,
MHL_TX_INT_CTRL_REG  396 drivers/gpu/drm/bridge/sii9234.c 	mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, 0, 0x30);
MHL_TX_INT_CTRL_REG  508 drivers/gpu/drm/bridge/sii9234.c 	mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, 0, 0x06);
MHL_TX_INT_CTRL_REG  539 drivers/gpu/drm/bridge/sii9234.c 	mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, 0, 1 << 5);
MHL_TX_INT_CTRL_REG  540 drivers/gpu/drm/bridge/sii9234.c 	mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, ~0, 1 << 4);