MFC_STATE1_MASTER_RUN_CONTROL_MASK  707 arch/powerpc/platforms/cell/spu_base.c 		tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
MFC_STATE1_MASTER_RUN_CONTROL_MASK  301 arch/powerpc/platforms/cell/spufs/backing_ops.c 	sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
MFC_STATE1_MASTER_RUN_CONTROL_MASK  312 arch/powerpc/platforms/cell/spufs/backing_ops.c 	sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
MFC_STATE1_MASTER_RUN_CONTROL_MASK  231 arch/powerpc/platforms/cell/spufs/hw_ops.c 	sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
MFC_STATE1_MASTER_RUN_CONTROL_MASK  242 arch/powerpc/platforms/cell/spufs/hw_ops.c 	sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
MFC_STATE1_MASTER_RUN_CONTROL_MASK  496 arch/powerpc/platforms/cell/spufs/switch.c 	spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |
MFC_STATE1_MASTER_RUN_CONTROL_MASK 1043 arch/powerpc/platforms/cell/spufs/switch.c 					MFC_STATE1_MASTER_RUN_CONTROL_MASK);
MFC_STATE1_MASTER_RUN_CONTROL_MASK 1055 arch/powerpc/platforms/cell/spufs/switch.c 					MFC_STATE1_MASTER_RUN_CONTROL_MASK);
MFC_STATE1_MASTER_RUN_CONTROL_MASK 1884 arch/powerpc/platforms/cell/spufs/switch.c 	spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);
MFC_STATE1_MASTER_RUN_CONTROL_MASK 2150 arch/powerpc/platforms/cell/spufs/switch.c 	    MFC_STATE1_MASTER_RUN_CONTROL_MASK |
MFC_STATE1_MASTER_RUN_CONTROL_MASK 3987 arch/powerpc/xmon/xmon.c 			tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;