MC_VM_MX_L1_TLB_CNTL  121 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
MC_VM_MX_L1_TLB_CNTL  122 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
MC_VM_MX_L1_TLB_CNTL  123 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
MC_VM_MX_L1_TLB_CNTL  125 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
MC_VM_MX_L1_TLB_CNTL  127 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
MC_VM_MX_L1_TLB_CNTL  128 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
MC_VM_MX_L1_TLB_CNTL  130 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
MC_VM_MX_L1_TLB_CNTL  302 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
MC_VM_MX_L1_TLB_CNTL  304 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 				MC_VM_MX_L1_TLB_CNTL,
MC_VM_MX_L1_TLB_CNTL  600 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
MC_VM_MX_L1_TLB_CNTL  601 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
MC_VM_MX_L1_TLB_CNTL  602 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
MC_VM_MX_L1_TLB_CNTL  603 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
MC_VM_MX_L1_TLB_CNTL  604 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
MC_VM_MX_L1_TLB_CNTL  721 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
MC_VM_MX_L1_TLB_CNTL  722 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
MC_VM_MX_L1_TLB_CNTL  723 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
MC_VM_MX_L1_TLB_CNTL  827 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
MC_VM_MX_L1_TLB_CNTL  828 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
MC_VM_MX_L1_TLB_CNTL  829 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
MC_VM_MX_L1_TLB_CNTL  830 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
MC_VM_MX_L1_TLB_CNTL  831 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
MC_VM_MX_L1_TLB_CNTL  965 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
MC_VM_MX_L1_TLB_CNTL  966 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
MC_VM_MX_L1_TLB_CNTL  967 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
MC_VM_MX_L1_TLB_CNTL  147 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
MC_VM_MX_L1_TLB_CNTL  148 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
MC_VM_MX_L1_TLB_CNTL  149 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
MC_VM_MX_L1_TLB_CNTL  151 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
MC_VM_MX_L1_TLB_CNTL  153 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
MC_VM_MX_L1_TLB_CNTL  154 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
MC_VM_MX_L1_TLB_CNTL  156 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
MC_VM_MX_L1_TLB_CNTL  347 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
MC_VM_MX_L1_TLB_CNTL  349 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 				MC_VM_MX_L1_TLB_CNTL,
MC_VM_MX_L1_TLB_CNTL 5445 drivers/gpu/drm/radeon/cik.c 	WREG32(MC_VM_MX_L1_TLB_CNTL,
MC_VM_MX_L1_TLB_CNTL 5567 drivers/gpu/drm/radeon/cik.c 	WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
MC_VM_MX_L1_TLB_CNTL 1286 drivers/gpu/drm/radeon/ni.c 	WREG32(MC_VM_MX_L1_TLB_CNTL,
MC_VM_MX_L1_TLB_CNTL 1371 drivers/gpu/drm/radeon/ni.c 	WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
MC_VM_MX_L1_TLB_CNTL 4297 drivers/gpu/drm/radeon/si.c 	WREG32(MC_VM_MX_L1_TLB_CNTL,
MC_VM_MX_L1_TLB_CNTL 4390 drivers/gpu/drm/radeon/si.c 	WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |