MC_SEQ_WR_CTL_D1_LP 5907 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		*out_reg = MC_SEQ_WR_CTL_D1_LP;
MC_SEQ_WR_CTL_D1_LP 6007 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
MC_SEQ_WR_CTL_D1_LP 1883 drivers/gpu/drm/radeon/btc_dpm.c 		*out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
MC_SEQ_WR_CTL_D1_LP 2038 drivers/gpu/drm/radeon/btc_dpm.c 	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
MC_SEQ_WR_CTL_D1_LP 4452 drivers/gpu/drm/radeon/ci_dpm.c 		*out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
MC_SEQ_WR_CTL_D1_LP 4650 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
MC_SEQ_WR_CTL_D1_LP 1000 drivers/gpu/drm/radeon/cypress_dpm.c 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2;
MC_SEQ_WR_CTL_D1_LP 2795 drivers/gpu/drm/radeon/ni_dpm.c 		*out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
MC_SEQ_WR_CTL_D1_LP 2891 drivers/gpu/drm/radeon/ni_dpm.c 	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
MC_SEQ_WR_CTL_D1_LP 5453 drivers/gpu/drm/radeon/si_dpm.c 		*out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
MC_SEQ_WR_CTL_D1_LP 5553 drivers/gpu/drm/radeon/si_dpm.c 	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));