MC_SEQ_WR_CTL_D1 5906 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	case MC_SEQ_WR_CTL_D1:
MC_SEQ_WR_CTL_D1 6007 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
MC_SEQ_WR_CTL_D1 1882 drivers/gpu/drm/radeon/btc_dpm.c 	case MC_SEQ_WR_CTL_D1 >> 2:
MC_SEQ_WR_CTL_D1 2038 drivers/gpu/drm/radeon/btc_dpm.c 	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
MC_SEQ_WR_CTL_D1 4451 drivers/gpu/drm/radeon/ci_dpm.c 	case MC_SEQ_WR_CTL_D1 >> 2:
MC_SEQ_WR_CTL_D1 4569 drivers/gpu/drm/radeon/ci_dpm.c 			case MC_SEQ_WR_CTL_D1:
MC_SEQ_WR_CTL_D1 4650 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
MC_SEQ_WR_CTL_D1 1001 drivers/gpu/drm/radeon/cypress_dpm.c 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2;
MC_SEQ_WR_CTL_D1 2794 drivers/gpu/drm/radeon/ni_dpm.c 	case MC_SEQ_WR_CTL_D1 >> 2:
MC_SEQ_WR_CTL_D1 2891 drivers/gpu/drm/radeon/ni_dpm.c 	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
MC_SEQ_WR_CTL_D1 5452 drivers/gpu/drm/radeon/si_dpm.c 	case MC_SEQ_WR_CTL_D1 >> 2:
MC_SEQ_WR_CTL_D1 5553 drivers/gpu/drm/radeon/si_dpm.c 	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));