MC_SEQ_WR_CTL_D0 5903 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	case MC_SEQ_WR_CTL_D0:
MC_SEQ_WR_CTL_D0 6006 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
MC_SEQ_WR_CTL_D0 1879 drivers/gpu/drm/radeon/btc_dpm.c 	case MC_SEQ_WR_CTL_D0 >> 2:
MC_SEQ_WR_CTL_D0 2037 drivers/gpu/drm/radeon/btc_dpm.c 	WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
MC_SEQ_WR_CTL_D0 4448 drivers/gpu/drm/radeon/ci_dpm.c 	case MC_SEQ_WR_CTL_D0 >> 2:
MC_SEQ_WR_CTL_D0 4560 drivers/gpu/drm/radeon/ci_dpm.c 			case MC_SEQ_WR_CTL_D0:
MC_SEQ_WR_CTL_D0 4649 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
MC_SEQ_WR_CTL_D0  997 drivers/gpu/drm/radeon/cypress_dpm.c 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2;
MC_SEQ_WR_CTL_D0 2791 drivers/gpu/drm/radeon/ni_dpm.c 	case MC_SEQ_WR_CTL_D0 >> 2:
MC_SEQ_WR_CTL_D0 2890 drivers/gpu/drm/radeon/ni_dpm.c 	WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
MC_SEQ_WR_CTL_D0 5449 drivers/gpu/drm/radeon/si_dpm.c 	case MC_SEQ_WR_CTL_D0 >> 2:
MC_SEQ_WR_CTL_D0 5552 drivers/gpu/drm/radeon/si_dpm.c 	WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));