MC_SEQ_RD_CTL_D1 5900 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	case MC_SEQ_RD_CTL_D1:
MC_SEQ_RD_CTL_D1 6009 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
MC_SEQ_RD_CTL_D1 1876 drivers/gpu/drm/radeon/btc_dpm.c 	case MC_SEQ_RD_CTL_D1 >> 2:
MC_SEQ_RD_CTL_D1 2036 drivers/gpu/drm/radeon/btc_dpm.c 	WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
MC_SEQ_RD_CTL_D1 4445 drivers/gpu/drm/radeon/ci_dpm.c 	case MC_SEQ_RD_CTL_D1 >> 2:
MC_SEQ_RD_CTL_D1 4652 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
MC_SEQ_RD_CTL_D1  993 drivers/gpu/drm/radeon/cypress_dpm.c 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2;
MC_SEQ_RD_CTL_D1 2788 drivers/gpu/drm/radeon/ni_dpm.c 	case MC_SEQ_RD_CTL_D1 >> 2:
MC_SEQ_RD_CTL_D1 2893 drivers/gpu/drm/radeon/ni_dpm.c 	WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
MC_SEQ_RD_CTL_D1 5446 drivers/gpu/drm/radeon/si_dpm.c 	case MC_SEQ_RD_CTL_D1 >> 2:
MC_SEQ_RD_CTL_D1 5555 drivers/gpu/drm/radeon/si_dpm.c 	WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));