MC_SEQ_RD_CTL_D0 5897 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	case MC_SEQ_RD_CTL_D0:
MC_SEQ_RD_CTL_D0 6008 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
MC_SEQ_RD_CTL_D0 1873 drivers/gpu/drm/radeon/btc_dpm.c 	case MC_SEQ_RD_CTL_D0 >> 2:
MC_SEQ_RD_CTL_D0 2035 drivers/gpu/drm/radeon/btc_dpm.c 	WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
MC_SEQ_RD_CTL_D0 4442 drivers/gpu/drm/radeon/ci_dpm.c 	case MC_SEQ_RD_CTL_D0 >> 2:
MC_SEQ_RD_CTL_D0 4651 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
MC_SEQ_RD_CTL_D0  989 drivers/gpu/drm/radeon/cypress_dpm.c 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D0 >> 2;
MC_SEQ_RD_CTL_D0 2785 drivers/gpu/drm/radeon/ni_dpm.c 	case MC_SEQ_RD_CTL_D0 >> 2:
MC_SEQ_RD_CTL_D0 2892 drivers/gpu/drm/radeon/ni_dpm.c 	WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
MC_SEQ_RD_CTL_D0 5443 drivers/gpu/drm/radeon/si_dpm.c 	case MC_SEQ_RD_CTL_D0 >> 2:
MC_SEQ_RD_CTL_D0 5554 drivers/gpu/drm/radeon/si_dpm.c 	WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));